DP83820 datasheet(5/87 Pages) NSC

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2.0 Pin Descriptions (Continued)

Media Independent Interface (MII) - and Gigabit Media Independent Interface (GMII).

Symbol

Pin No(s)

Direction

Description

COL

170

Collision Detect: The COL signal is asserted high asynchronously by the

external PMD upon detection of a collision on the medium. It will remain

asserted as long as the collision condition persists.

CRS/SIGDET

169

Carrier Sense: This signal is asserted high asynchronously by the external

physical unit upon detection of a non-idle medium.

Signal Detect: In TBI mode, this signal is used to bring in the Signal Detect

indication from the Phy.

MDC

138

Management Data Clock: Clock signal with a maximum rate of 2.5 MHz used

to transfer management data for the external PMD on the MDIO pin.

MDIO

139

I/O

Management Data I/O: Bidirectional signal used to transfer management

information for the external PMD. Requires an external 4.7 K

Ω pullup resistor.

RXCLK/

RXPMACLK1

156

Receive Clock: A continuous clock, sourced by an external PMD device, that is

recovered from the incoming data. During 1000 Mb/s mode RX_CLK is 125

MHz, during 100 Mb/s operation RX_CLK is 25 MHz and during 10 Mb/s this is

2.5 MHz.

Receive PMA Clock 1: In TBI mode, this 62.5Mhz clock is used in conjunction

with RXPMACLK0 to clock 10-bit TBI data into the DP83820. The rising edge of

RXPMACLK1 clocks the even-numbered bytes.

RXD7,

RXD6,

RXD5,

RXD4,

RXD3,

RXD2,

RXD1,

RXD0

166,

165,

164,

163,

160,

159,

158,

157

Gigabit Receive Data: This is a group of 8 signals, sourced from an external

PMD, that contains data aligned on byte boundaries and are driven

synchronous to the RX_CLK. RXD7 is most significant bit.

Receive Data: This is a group of 4 signals, sourced from an external PMD, that

contains data aligned on nibble boundaries and are driven synchronous to the

RX_CLK. RXD3 is the most significant bit and RXD0 is the least significant bit.

RXD7 through RXD4 are not used in this mode.

TBI Receive Data: In TBI mode, these bits are the lower 8 bits of the 10-bit TBI

Receive data.

RXDV/RXD8

167

Receive Data Valid: This indicates that the external PMD is presenting

recovered and decoded nibbles on the RXD signals, and that RX_CLK is

synchronous to the recovered data in 100 Mb/s operation. This signal will

encompass the frame, starting with the Start-of-Frame delimiter (JK) and

excluding any End-of-Frame delimiter (TR).

TBI Receive Data: In TBI mode, this is RXD8 of the 10-bit TBI Receive data.

RXER/RXD9

168

Receive Error: This signal is asserted high synchronously by the external PMD

whenever it detects a media error and RXDV is asserted in 100 Mb/s or 1000

Mb/s operation.

TBI Receive Data: In TBI mode, this is RXD9 of the 10-bit TBI Receive data.

RXEN

171

Receive Output Enable: This pin is used to disable an external PMD while the

BIOS ROM is being accessed.

TXCLK/

RXPMACLK0

155

MII Transmit Clock: A continuous clock that is sourced by the external PMD.

During 100 Mb/s operation this is 25 MHz +/- 100 ppm. During 10 Mb/s

operation this clock is 2.5 MHz +/- 100 ppm.

Receive PMA Clock 0: In TBI mode, this 62.5Mhz clock is used in conjunction

with RXPMACLK1 to clock 10-bit TBI data into the DP83820. The rising edge of

RXPMACLK0 clocks the odd-numbered bytes.

DP83820 Datasheet(PDF) 5 Page - National Semiconductor (TI)

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