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PC87393F Datasheet(PDF) 24 Page - National Semiconductor (TI) |
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PC87393F Datasheet(HTML) 24 Page - National Semiconductor (TI) |
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24 / 148 page  1.0 Signal/Pin Connection and Description (Continued) 24 www.national.com 1.6 INTERNAL PULL-UP AND PULL-DOWN RESISTORS The signals listed in Table 4 can optionally support internal pull-up (PU) and/or pull-down (PD) resistors. See Section 9.3 for the values of each resistor type. Table 4. Internal Pull-Up and Pull-Down Resistors XIOWR 82, 73 O O3/6 VDD I/O Write. Active (low) level indicates I/O write cycle on the X-Bus Extension. This signal is for devices that require separate read/write inputs for memory and I/O. XD7-0 96, 97, 98, 99, 100, 1, 2, 3 I/O INTS/O3/6 VDD Data Bus XA19-0 74-95 O O3/6 VDD Address Bus XCS1-0 73, 72 O O3/6 VDD Chip Select. These signals control the selection of up to two chips residing on the X-Bus Extension. XSTB2-0 87, 90, 91 OO3/6 VDD Assert Strobe. These signals control the selection of up to three external latch devices for X-Bus Latched Address Mode transactions. XRDY 72, 35 I INTS VDD I/O Ready. This signal indicates to the PC87393 to extend the access cycles. PIRQA-D 87-84 I INTS VDD Parallel Interrupt. Convert parallel interrupts into serial interrupts by means of the Interrupt Serializer (The interrupt number associated with each signal is a part of the system configuration.) Signal Pin/s Type Comments Game Port (GMP) (PC87393 and PC87393F) JOYABTN0 PU25 Programmable JOYABTN1 PU25 Programmable JOYBBTN0 PU25 Programmable JOYBBTN1 PU25 Programmable General-Purpose Input/Output (GPIO) Ports (PC87392, PC87393 and PC87393F) GPIO00-07 PU25 Programmable GPIO10-17 PU25 Programmable GPIO20-27 PU25 Programmable GPIO30-37 PU25 Programmable Musical Instrument Digital Interface (MIDI) Port (PC87393 and PC87393F) MDRX PU25 Programmable Strap Configuration BADDR PD40 Strap TEST PD15 Strap Signal Pin/s I/O Buffer Type Power Well Description |
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