PC87393F datasheet(37/148 Pages) NSC

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2.0 Device Architecture and Configuration (Continued)

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LPC-FWH Address Translation: The address field in the LPC-FWH transaction is constructed of eight nibbles. The first

seven nibbles correspond to the first LS seven address nibbles (A27-A0), as follows: the first incoming nibble corresponds

to addresses A27 - A24, the second to A23 - A20, and so forth until the seventh nibble, which corresponds to A3 - A0. In-

coming nibble eight is ignored. The MS bits of the 32-bit addresses are ’1111’ (A31 - A28).

2.8.2

CLKRUN Functionality

The PC8739x supports the CLKRUN I/O signal, whose use is highly recommended in portable systems. This signal is im-

plemented according to the specification in

PCI Mobile Design Guide, Revision 1.1, December 18, 1998. The PC8739x sup-

ports operation with both a slow and stopped clock in ACPI state S0 (the system is active but is not being accessed). The

PC8739x drives the CLKRUN signal low to force the LPC bus clock into full speed operation in the following cases:

An IRQ is pending internally, waiting to be sent through the serial IRQ.

A DMA request or abort is pending internally, waiting to be sent through the serial DMA.

Note: When the CLKRUN signal is not in use, the PC8739x assumes valid clock on the CLKIN pin.

2.8.3

LPCPD Functionality

The PC8739x supports the LPCPD input. This signal is used in case the VDD chip supply is not shared by all residents of

the LPC bus. The LPCPD signal conforms with Intel’s

LPC Interface Specification, Revision 1.00. Note that if the PC8739x

power supply exists while LPCPD is active, it is not mandatory to reset the PC8739x when LPCPD is de-asserted.

2.9

The following abbreviations are used to indicate the Register Type:

R/W = Read/Write

R = Read from a speciﬁc address returns the value of a speciﬁc register. Write to the same address is to a different

W=Write

RO = Read Only

R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect.

2.10 SUPERI/O CONFIGURATION REGISTERS

This section describes the SuperI/O configuration and ID registers (those registers with first level indexes in the range of 20h

- 2Eh). See Table 15 for a summary and directory of these registers.

Note: Set the configuration registers to enable functions or signals that are relevant to the specific device. The val-

ues of fields that select functions, or signals, that are excluded from a specific device are treated as reserved and

should not be selected.

Table 15. SuperI/O Conﬁguration Registers

Index

Mnemonic

Power Well

Type

Section

20h

SID

SuperI/O ID

VDD

2.10.1

21h

SIOCF1

SuperI/O Conﬁguration 1

VDD

R/W

2.10.2

22h

SIOCF2

SuperI/O Conﬁguration 2

VDD

R/W

2.10.3

23h

SIOCF3

SuperI/O Conﬁguration 3

VDD

R/W

2.10.4

24h

SIOCF4

SuperI/O Conﬁguration 4

VDD

R/W

2.10.5

25h

SIOCF5

SuperI/O Conﬁguration 5

VDD

R/W

2.10.6

26h

SIOCF6

SuperI/O Conﬁguration 6

VDD

R/W

2.10.7

27h

SRID

SuperI/O Revision ID

VDD

2.10.8

28h

SIOCF8

SuperI/O Conﬁguration 8

VDD

R/W

2.10.9

29h

SIOCF9

SuperI/O Conﬁguration 9

VDD

R/W

2.10.10

2Ah

SIOCFA

SuperI/O Conﬁguration A

VDD

R/W

2.10.11

2Bh - 2Fh

Reserved exclusively for National use

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