PC87393F datasheet(52/148 Pages) NSC

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2.0 Device Architecture and Configuration (Continued)

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2.12.3

Parallel Port Configuration Register

This register is reset by hardware to F2h.

Location:

Index F0h

Type:

R/W

Bit

76543210

Name

Parallel Port Mode Select

Extended

Access

Reserved

PP Reflect-

ed Input

Signals

Power

Mode

Control

TRI-STATE

Control

Reset

11110010

Bit

Description

7-5

Parallel Port Mode Select

000:

SPP Compatible mode. PD7-0 are always output signals.

001:

SPP Extended mode. PD7-0 direction is controlled by software.

010:

EPP 1.7 mode

011:

EPP 1.9 mode

100:

ECP mode (IEEE1284 register set), with no support for EPP mode.

101:

Reserved

110:

Reserved

111:

ECP mode (IEEE1284 register set), with EPP mode selectable as mode 4.

Selection of EPP 1.7 or 1.9 in ECP mode 4 is controlled by bit 4 of the Control2 conﬁguration register of the

parallel port at offset 02h.

Extended Register Access

0: Registers at base (address) + 403h, base + 404h and base + 405h are not accessible (reads and writes are ignored).

1: Registers at base (address) + 403h, base + 404h and base + 405h are accessible. This option supports run-

time conﬁguration within the Parallel Port address space.

Reserved

PP Reflected Input Signals. When the parallel port input signal is disconnected by the PPM, the input signals

reflected by the STR register assume one of the following values:

0: BUSY=1,PE=0,SLCT=0, ACK = 1 (default)

1: BUSY=1,PE=1,SLCT=1, ACK = 1.

Power Mode Control. When the logical device is active:

0: Parallel port clock disabled. ECP modes and EPP time-out are not functional when the logical device is active.

Registers are maintained.

1: Parallel port clock enabled. All operation modes are functional when the logical device is active (default).

TRI-STATE Control. When enabled and the device is inactive, the logical device output pins are in TRI-STATE.

0: Disabled (default)

1: Enabled

PC87393F Datasheet(PDF) 52 Page - National Semiconductor (TI)

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