PC87393F datasheet(51/148 Pages) NSC

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2.0 Device Architecture and Configuration (Continued)

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Table 19. Parallel Port Registers at Second Level Offset

2.12.2

Logical Device 1 (PP) Configuration

Table 20 lists the configuration registers which affect the Parallel Port. Only the last register (F0h) is described here. See

Sections 2.2.3 and 2.2.4 for descriptions of the others.

Table 20. Parallel Port Conﬁguration Registers

Offset

Mnemonic

Type

00h

Control0

R/W

Extended Control 0

02h

Control2

R/W

Extended Control 1

04h

Control4

R/W

Extended Control 4

05h

PP Confg0

R/W

Conﬁguration 0

Index

Conﬁguration Register or Action

Type

Reset

30h Activate. See also bit 0 of the SIOCF1 register.

R/W

00h

60h Base Address MSB register. Bits 7-3 (for A15-11) are read only, 00000b. Bit 2 (for

A10) should be 0b.

R/W

02h

61h Base Address LSB register. Bits 1 and 0 (A1 and A0) are read only, 00b. For ECP

Mode 4 (EPP) or when using the Extended registers, bit 2 (A2) should also be 0b.

R/W

78h

70h Interrupt Number and Wake-Up on IRQ Enable register

R/W

07h

71h Interrupt Type

Bits 7-2 are read only.

Bit 1 is a read/write bit.

Bit 0 is read only. It reﬂects the interrupt type dictated by the Parallel Port operation

mode. This bit is set to 1 (level interrupt) in Extended Mode and cleared (edge

interrupt) in all other modes.

R/W

02h

74h DMA Channel Select

R/W

04h

75h Report no second DMA assignment

04h

F0h Parallel Port Conﬁguration register

R/W

F2h

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