PC87393F datasheet(60/148 Pages) NSC

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2.0 Device Architecture and Configuration (Continued)

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2.15.6

GPIO Event Routing Register

This register enables the routing of the GPIO event to IRQ and/or SMI signals. It is implemented only for ports 0,1 which

have event detection capability. This register is reset by hardware to 00h.

Location:

Index F2h

Type:

R/W

Pull-Up Control. This bit is used to enable/disable the internal pull-up capability of the corresponding GPIO pin.

It supports open-drain output signals with internal pull-ups and TTL input signals.

0: Disabled

1: Enabled (default)

Output Type. This bit controls the output buffer type (open-drain or push-pull) of the corresponding GPIO pin.

0: Open-drain (default)

1: Push-pull

Output Enable. This bit indicates the GPIO pin output state. It has no effect on the input path.

0: TRI-STATE (default)

1: Output enabled

Bit

76543210

Name

Reserved

Enable SMI

Routing

Enable IRQ

Routing

Reset

00000001

Bit

Description

7-2

Reserved

Enable SMI Routing

0: Disabled (default)

1: Enabled

Enable IRQ Routing

0: Disabled

1: Enabled (default)

Bit

Description

PC87393F Datasheet(PDF) 60 Page - National Semiconductor (TI)

PC87393F Datasheet(HTML) 60 Page - National Semiconductor (TI)

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