PC87393F datasheet(47/148 Pages) NSC

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2.0 Device Architecture and Configuration (Continued)

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2.11 FLOPPY DISK CONTROLLER (FDC) CONFIGURATION

2.11.1

General Description

The generic FDC is a standard FDC with a digital data separator, and is DP8473 and N82077 software compatible. The PC8739x

FDC supports 14 of the 17 standard FDC signals described in the generic Floppy Disk Controller (FDC) chapter, including:

FM and MFM modes are supported. To select either mode, set bit 6 of the ﬁrst command byte when writing to/read-

ing from a diskette, where:

0 = FM mode

1 = MFM mode

A logic 1 is returned for all ﬂoating (TRI-STATE) FDC register bits upon LPC I/O read cycles.

Exceptions to standard FDC support include:

Automatic media sense is supported by MSEN1-0 pins only on FDC signals routed to the PPM functional block (on

the Parallel Port)

DRATE1 is supported only on FDC signals routed to the PPM functional block (on the Parallel Port).

Table 16 lists the FDC functional block registers.

Table 16. FDC Registers

2.11.2

Logical Device 0 (FDC) Configuration

Table 17 lists the configuration registers which affect the FDC. Only the last two registers (F0h and F1h) are described here.

See Sections 2.2.3 and 2.2.4 for descriptions of the others.

Table 17. FDC Conﬁguration Registers

Offset1

1. From the 8-byte aligned FDC base address.

Mnemonic

Type

00h

SRA

Status A

01h

SRB

Status B

02h

DOR

Digital Output

R/W

03h

TDR

Tape Drive

R/W

04h

MSR

Main Status

DSR

Data Rate Select

05h

FIFO

Data (FIFO)

R/W

06h

N/A

07h

DIR

Digital Input

CCR

Conﬁguration Control

Index

Conﬁguration Register or Action

Type

Reset

30h

Activate. See also bit 0 of the SIOCF1 register and bit 0 of the SIOCF6 register. R/W

00h

60h

Base Address MSB register. Bits 7-3 (for A15-11) are read only, 00000b.

R/W

03h

61h

Base Address LSB register. Bits 2 and 0 (for A2 and A0) are read only, 00b.

R/W

F2h

70h

Interrupt Number and Wake-Up on IRQ Enable register

R/W

06h

71h

Interrupt Type. Bit 1 is read/write; other bits are read only.

R/W

03h

74h

DMA Channel Select

R/W

02h

75h

Report no second DMA assignment

04h

F0h

FDC Conﬁguration register

R/W

24h

F1h

Drive ID register

R/W

00h

PC87393F Datasheet(PDF) 47 Page - National Semiconductor (TI)

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