PC87393F datasheet(65/148 Pages) NSC

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2.0 Device Architecture and Configuration (Continued)

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2.19 X-BUS CONFIGURATION

This section applies to the PC87393 and PC87393F only. FWH-related descriptions apply to the PC87393F only.

2.19.1

Logical Device 15 (X-Bus) Configuration

Table 28 lists the configuration registers that affect the X-Bus functional block. The X-Bus base address registers point to

the X-Bus registers described in the X-Bus chapter. The memory space to which the X-Bus responds is defined by the con-

figuration registers in the following sections. See Sections 2.2.3 and 2.2.4 for a detailed description of the others.

Table 28. X-Bus Conﬁguration Registers

2.19.2

X-Bus I/O Range Programming

LPC I/O transactions can be forwarded to the PC8739x X-Bus. The X-Bus I/O configuration registers define the map of ad-

dresses to be forwarded. The PC8739x provides five, individually enabled I/O zones. Each zone generates an internal select

signal that is sent to the X-Bus functional block. The mapping of the internal select signals to the PC8739x XCS0-1 signals

is controlled by the X-Bus. See Section 7.3 for further details.

The supported I/O zones are:

Keyboard controller (KBC) - legacy 60h, 64h addresses and an alternate location

Power Management & Embedded Controller (PM) - legacy 62h, 66h and an alternate location

Real Time Clock (RTC) - legacy 70h, 71h and two alternate locations

User-Deﬁned I/O Zone (UDIZ) - speciﬁed using the zone size (2n where n is 1 through 8) and start address (must be

aligned with the block size)

Debug Port Address Enable (TST) - This zone is for debug use only.

These decoded I/O zones are determined by the following four registers: X-Bus I/O Configuration, X-Bus I/O Zone Base

Address High and Low Byte, and X-Bus I/O Size Configuration. When a zone (e.g. KBC, PM or RTC) is enabled but is not

associated with any select signal in the X-Bus interface, a value of 00h is read and data written is ignored.

Index

Conﬁguration Register or Action

Type

Reset

30h

Activate. When bit 0 is cleared, the registers of this logical device are not accessible.

R/W

00h

60h

Base Address MSB register

R/W

00h

61h

Base Address LSB register. Bits 3-0 (for A3-A0) are read only, 0000b.

Varies per

bit

00h

70h

Interrupt Number and wake-up on IRQ enable.

00h

71h

Interrupt Type.

00h

74h

Report no DMA assignment

04h

75h

Report no DMA assignment

04h

F0h

X-Bus I/O Conﬁguration register

R/W

00h

F1h

X-Bus I/O Base Address High Byte register

R/W

00h

F2h

X-Bus I/O Base Address Low Byte register

R/W

00h

F3h

X-Bus I/O Size Conﬁguration register

R/W

00h

F4h

X-Bus Memory Conﬁguration register

R/W

00h

F5h

X-Bus Memory Base Address High Byte register

R/W

00h

F6h

X-Bus Memory Base Address Low Byte register

R/W

00h

F7h

X-Bus Memory Size Conﬁguration register

R/W

00h

F8h

X-Bus PIRQA and PIRQB Mapping register

R/W

00h

F9h

X-Bus PIRQC and PIRQD Mapping register

R/W

00h

PC87393F Datasheet(PDF) 65 Page - National Semiconductor (TI)

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