PC87393F datasheet(74/148 Pages) NSC

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3.0 General-Purpose Input/Output (GPIO) Port (Continued)

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3.3

EVENT HANDLING AND SYSTEM NOTIFICATION

The enhanced GPIO port supports system notification based on event detection. This functionality is based on six configu-

ration bits and a bit slice of runtime registers GPEVEN and GPEVST. The configuration and operation of the event detection

capability is shown in Figure 10. The operation of system notification is illustrated in Figure 11.

Figure 10. Event Detection

3.3.1

Event Configuration

Each pin in the GPIO port is a potential input event source. The event detection can trigger a system notification upon pre-

determined behavior of the source pin. The GPCFG register determines the event detection trigger type for the system no-

tification.

Event Type and Polarity

Two trigger types of event detection are supported: edge and level. An edge event may be detected upon a source pin tran-

sition either from high to low or low to high. A level event may be detected when the source pin is in active level. The trigger

type is determined by Event Type (bit 4 of the GPCFG register). The direction of the transition (for edge) or the polarity of

the active level (for level) is determined by Event Polarity (bit 5 of the GPCFG register).

Event Debounce Enable

The input signal can be debounced for about 15 msec before entering the detector. The signal state is transferred to the

detector only after a debouncing period during which the signal has no transitions, to ensure that the signal is stable. The

debouncer adds 15 msec delay to both assertion and de-assertion of the event pending indicator. Therefore, when working

with a level event and system notification by either SMI or IRQ, it is recommended to disable the debounce if the delay in

the SMI/IRQ de-assertion is not acceptable. The debounce is controlled by Event Debounce Enable (bit 6 of the GPCFG

3.3.2

System Notification

System notification on GPIO-triggered events is by means of assertion of one or more of the following output pins:

Interrupt Request (via the device’s Bus Interface)

System Management Interrupt (SMI, via the device’s Bus Interface)

The system notiﬁcation for each GPIO pin is controlled by the corresponding bits in the GPEVEN and GPEVR registers.

System notification by a GPIO pin is enabled if the corresponding bit of the GPEVEN register is set to 1. The corresponding

bits in the GPEVR register select which means of system notification the detected event is routed to. The event routing

mechanism is described in Figure 11.

Event

Enable

Event Polarity

Detected

Enabled Events

GPIO Pins

Input

Debouncer

Event

Internal

Bus

Level =1

R/W 1 to Clear

Status

Rising Edge or

Rising

Edge

Detector

from other

High Level =1

GPIO Pin Conﬁguration Register

Event Type

Event

Debounce

Enable

R/W

Bit 6

Bit 5

Bit 4

Indicator

Pending

PC87393F Datasheet(PDF) 74 Page - National Semiconductor (TI)

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