PC87393F datasheet(70/148 Pages) NSC

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2.0 Device Architecture and Configuration (Continued)

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2.19.10 X-Bus Memory Base Address Low Byte Register

This register describes the low byte for the user-defined memory zone mapped to the X-Bus (decoded as bits 23 to 16 of

the 32-bit address range; bits 15 to 0 are 0). This register is reset by hardware to 00h.

Location:

Index F6h

Type:

R/W

2.19.11 X-Bus Memory Size Configuration Register

This register defines the size of the user-defined memory zone mapped to the X-Bus. This register is reset by hardware to

00h.

Location:

Index F7h

Type:

R/W

Bit

76543210

Name

User-Defined Memory Zone Address Low

Reset

00000000

Bit

Description

7-0

User-Deﬁned Memory Zone Address Low. Deﬁnes the lower 8 bits of the user-deﬁned memory block base

address. The base address should be aligned on the selected block size.

Bit

76543210

Name

Reserved

User-Defined Memory Zone Size

Reset

00000000

Bit

Description

7-4

Reserved

3-0

User-Deﬁned Memory Zone Size. Deﬁnes the size in bytes of the zone window. The size is deﬁned as a power

of two using the equation: NumOfBytes = 2n(User-Deﬁned Memory Zone size+16). The zone must always be

aligned to the window size (i.e., for a 128 Kbyte window, the 17 LSBs of the address should be zero.

Bits

Size (Bytes)

3 2 1 0

0 0 0 0

64K (default)

...

1000

16M

Other

Reserved

PC87393F Datasheet(PDF) 70 Page - National Semiconductor (TI)

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