PC87393F datasheet(48/148 Pages) NSC

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2.0 Device Architecture and Configuration (Continued)

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2.11.3

FDC Configuration Register

This register is reset by hardware to 24h.

Location:

Index F0h

Type:

R/W

Bit

76543210

Name

Four-Drive

Encode

Enable

TDR

Mode

DENSEL

Polarity

Control

FDC 2Mbps

Enable

Write

Protect

PC-AT or

PS/2 Drive

Mode Select

Reserved

TRI-STATE

Control

Reset

00100100

Bit

Description

Four-Drive Encode Enable

0: Two ﬂoppy drives are directly controlled by DR1-0, MTR1-0.

1: Four ﬂoppy drives are controlled with the aid of an external decoder.

TDR Register Mode

0: PC-AT compatible drive mode; i.e., bits 7-2 of the TDR are 111111b (default)

1: Enhanced drive mode

DENSEL Polarity Control

0: Active low for 500 Kbps, or 1 or 2 Mbps data rates

1: Active high for 500 Kbps, or 1 or 2 Mbps data rates (default)

FDC 2Mbps Enable. This bit is set only when a 2Mbps drive is used.

0: 2Mbps disabled and the FDC clock is 24 MHz (default)

1: 2Mbps enabled and the FDC clock is 48 MHz

Write Protect. This bit allows forcing of write protect functionality by software. When set, writes to the floppy

disk drive are disabled. This effect is identical to WP when it is active.

0: Write protected according to WP signal (default)

1: Write protected regardless of value of WP signal

PC-AT or PS/2 Drive Mode Select

0: PS/2 drive mode

1: PC-AT drive mode (default)

Reserved

TRI-STATE Control. When enabled and the device is inactive, the logical device output pins are in TRI-STATE.

0: Disabled (default)

1: Enabled

PC87393F Datasheet(PDF) 48 Page - National Semiconductor (TI)

PC87393F Datasheet(HTML) 48 Page - National Semiconductor (TI)

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