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PC87393F Datasheet(PDF) 68 Page - National Semiconductor (TI) |
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PC87393F Datasheet(HTML) 68 Page - National Semiconductor (TI) |
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68 / 148 page ![]() 2.0 Device Architecture and Configuration (Continued) 68 www.national.com 2.19.5 X-Bus I/O Base Address High Byte Register This register describes the high byte for the user-defined I/O zone mapped to the X-Bus. This register is reset by hardware to 00h. Location: Index F1h Type: R/W 2.19.6 X-Bus I/O Base Address Low Byte Register This register describes the low byte for the user-defined I/O zone mapped to the X-Bus. This register is reset by hardware to 00h. Location: Index F2h Type: R/W 2.19.7 X-Bus I/O Size Configuration Register This register defines the size of the user-defined I/O zone mapped to the X-Bus. This register is reset by hardware to 00h. Location: Index F3h Type: R/W Bit 76543210 Name User-Defined Zone Address High Reset 00000000 Bit Description 7-0 User-Defined Zone Address High. Defines the higher 8 bits of the user-defined I/O block base address. The base address should be aligned on the selected block size. Bit 76543210 Name User-Defined Zone Address Low Reset 00000000 Bit Description 7-0 User-Defined Zone Address Low. Defines the lower 8 bits of the user-defined I/O block base address. The base address should be aligned on the selected block size. Bit 76543210 Name Reserved User-Defined I/O Zone Size Reset 00000000 Bit Description 7-4 Reserved 3-0 User-Defined I/O Zone Size. Defines the size in bytes of the zone window. The size is defined as a power of two using the equation: NumOfBytes = 2n(User-Defined I/O Zone size). The zone must always be aligned to the window size (i.e., for a 128 byte window, the 7 LSBs of the address are zero). Bits Size (Bytes) 3 2 1 0 0 0 0 0 1 (default) ... 1000 256 Other Reserved |
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