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PC87393F Datasheet(PDF) 61 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part # PC87393F
Description  100-Pin LPC SuperI/O Devices for Portable Applications
PDF  148 Pages
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

PC87393F Datasheet(HTML) 61 Page - National Semiconductor (TI)

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2.0 Device Architecture and Configuration (Continued)
61
www.national.com
2.16 WATCHDOG TIMER (WDT) CONFIGURATION
2.16.1
Logical Device 10 (WDT) Configuration
Table 25 lists the configuration registers which affect the WATCHDOG Timer. Only the last register (F0h) is described here.
See Sections 2.2.3 and 2.2.4 for a detailed description of the others.
Table 25. WDT Configuration Registers
2.16.2
WATCHDOG Timer Configuration Register
This register is reset by hardware to 02h.
Location:
Index F0h
Type:
R/W
Index
Configuration Register or Action
Type
Reset
30h
Activate. When bit 0 is cleared, the registers of this logical device are not
accessible.
R/W
00h
60h
Base Address MSB register
R/W
00h
61h
Base Address LSB register. Bits 1 and 0 (for A1 and A0) are read only, 00b.
R/W
00h
70h
Interrupt Number (for routing the WDO signal) and Wake-Up on IRQ Enable
register.
R/W
00h
71h
Interrupt Type. Bit 1 is read/write. Other bits are read only.
R/W
03h
74h
Report no DMA assignment
RO
04h
75h
Report no DMA assignment
RO
04h
F0h
WATCHDOG Timer Configuration register
R/W
02h
Bit
76543210
Name
Reserved
Output
Type
Internal
Pull-Up
Enable
Power
Mode
Control
TRI-STATE
Control
Reset
00000010
Bit
Description
7-4
Reserved
3
Output Type. This bit controls the buffer type (open-drain or push-pull) of the WDO pin.
0: Open-drain (default)
1: Push-pull
2
Internal Pull-Up Enable. This bit controls the internal pull-up resistor on the WDO pin.
0: Disabled (default)
1: Enabled
1
Power Mode Control
0: Low power mode:
WATCHDOG Timer clock disabled. WDO output signal is set to 1. Registers are accessible and maintained
(unlike Active bit in Index 30h that also prevents access to WATCHDOG Timer registers).
1: Normal power mode:
WATCHDOG Timer clock enabled. WATCHDOG Timer is functional when the logical device is active (default).
0
TRI-STATE Control. When enabled and the device is inactive, the logical device output pins are in TRI-STATE.
0: Disabled (default)
1: Enabled



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