PC87393F datasheet(64/148 Pages) NSC

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2.0 Device Architecture and Configuration (Continued)

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2.18 MIDI PORT (MIDI) CONFIGURATION

This section applies to the PC87393 and PC87393F only.

2.18.1

Logical Device 12 (MIDI) Configuration

Table 26 lists the configuration registers which affect the MIDI Port. Only the last register (F0h) is described here. See Sec-

tions 2.2.3 and 2.2.4 for a detailed description of the others.

Table 27. MIDI Conﬁguration Registers

2.18.2

MIDI Port Configuration Register

This register is reset by hardware to 00h.

Location:

Index F0h

Type:

R/W

Usage Hints: To operate MIDI enhanced features, make sure to locate its base address within the LPC Wide Generic ad-

dress range.

When bit 3 of the MIDI configuration register is set to 0 (default), the MIDI operates in Legacy mode. In this mode, only the

MIDI IN, MIDI OUT, MIDI Status and MIDI Command registers of the MIDI are user-accessible.

When bit 3 of the MIDI configuration register is set to 1, the MIDI is operated in Enhanced mode. In this condition, all the

registers listed in the MIDI chapter are accessible.

Index

Conﬁguration Register or Action

Type

Reset

30h

Activate. When bit 0 is cleared, the registers of this logical device are not accessible.

R/W

00h

60h

Base Address MSB register

R/W

03h

61h

Base Address LSB register. Bit 0 (for A0) is read only, 0b.

Varies per bit

30h

70h

Interrupt Number and wake-up on IRQ enable.

R/W

00h

71h

Interrupt Type. Bit 1 is read/write. Other bits are read only.

R/W

03h

74h

Report no DMA assignment

04h

75h

Report no DMA assignment

04h

F0h

MIDI Port Conﬁguration register

R/W

00h

Bit

7654

210

Name

Reserved

MIDI

Enhanced

Mode Enable

Internal

Pull-Up

Enable

Reserved

TRI-STATE

Control

Reset

0000

000

Bit

Description

7-4

Reserved

MIDI Enhanced Mode Enable. See Usage Hints below.

0: Disabled (default)

1: Enabled

Internal Pull-Up Enable. This bit controls the internal pull-up resistor on pin 83 (GPIO32/MDRX).

0: Disabled (default)

1: Enabled

Reserved

TRI-STATE Control. When enabled and the device is inactive, the logical device output pins are in TRI-STATE.

0: Disabled (default)

1: Enabled

PC87393F Datasheet(PDF) 64 Page - National Semiconductor (TI)

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