PC87393F datasheet(67/148 Pages) NSC

67 / 148 page

2.0 Device Architecture and Configuration (Continued)

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Type:

R/W

Bit

76543210

Name

User-

Defined I/O

Zone

Enable

TST

Address

Enable

RTC Address Enable

PM Address Enable

KBC Address Enable

Reset

00000000

Bit

Description

User-Deﬁned I/O Zone Enable. This bit enables the mapping of the User-Deﬁned I/O zone to the X-Bus space.

The zone base address and size are deﬁned by the X-Bus I/O Base Address High Byte register, X-Bus I/O Base

Address Low Byte register and the X-Bus I/O Size Conﬁguration register.

0: Disabled (default)

1: Enabled

TST (Debug Port) Address Enable. When set, enables the mapping of I/O address 80h to the X-Bus space.

0: Disabled (default)

1: Enabled

5-4

RTC Address Enable. This bit controls the mapping of the RTC I/O address to the X-Bus space.

Bits

Mapping (hex)

5 4

0 0

Disabled (default)

0 1

70, 71

1 0

370, 371

1 1

70, 71, 72, 73

3-2

PM Address Enable. This bit controls the mapping of the PM I/O address to the X-Bus space.

Bits

Mapping (hex)

3 2

0 0

Disabled (default)

0 1

62, 66

1 0

362, 366

1 1

Reserved

1-0

KBC Address Enable. This bit controls the mapping of the KBC I/O address to the X-Bus space.

Bits

Mapping (hex)

1 0

0 0

Disabled (default)

0 1

60, 64

1 0

360, 364

1 1

Reserved

PC87393F Datasheet(PDF) 67 Page - National Semiconductor (TI)

PC87393F Datasheet(HTML) 67 Page - National Semiconductor (TI)

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