PC87393F datasheet(140/148 Pages) NSC

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9.0 Device Characteristics (Continued)

140

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9.4.3

LCLK and LRESET

Symbol

Parameter

Min

Max

Units

tCYC

1. The PCI may have any clock frequency between nominal DC and 33

MHz. Device operational parameters at frequencies under 16 MHz

may be guaranteed by design rather than by testing. The clock fre-

quency may be changed at any time during the operation of the sys-

tem as long as the clock edges remain “clean” (monotonic) and the

minimum cycle and high and low times are not violated. The clock

may only be stopped in a low state.

LCLK Cycle Time

tHIGH

LCLK High Time

tLOW

LCLK Low Time

LCLK Slew Rate2

2. Rise and fall times are speciﬁed in terms of the edge rate measured in

V/ns. This slew rate must be met across the minimum peak-to-peak

portion of the clock wavering as shown below.

V/ns

LRESET Slew Rate3

3. The minimum LRESET slew rate applies only to the rising (de-assertion)

edge of the reset signal, and ensures that system noise cannot ren-

der an otherwise a monotonic signal to appear to bounce in the

switching range.

mV/ns

0.6 VDD

0.2 VDD

0.5 VDD

0.4 VDD

0.3 VDD

0.4 VDD p-to-p

(minimum)

tHIGH

tLOW

3.3 V Clock

tCYC

PC87393F Datasheet(PDF) 140 Page - National Semiconductor (TI)

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