PC87591L datasheet(230/437 Pages) NSC

230 / 437 page

Embedded Controller Modules (Continued)

www.national.com

230

Revision 1.07

Flash Memory Control Register (FLCR)

This register controls the on-chip flash operation modes. It is cleared (0016) on reset. The core can write this register only

when HLOCK bit in SMCCST register is 0 (see Section 5.3.9 on page 307). Otherwise, writes are ignored.

Location: 00 F8C016

Type: R/W

Bit

76543210

Name

SMER

PMER

IENPROG

Reserved

LOWPWR

Reset

00000000

Bit

Name

Reserved

DISVRF

Reset

00000000

Bit

Description

LOWPWR (Low Power Mode).

On-chip flash is in Normal mode

On-chip flash is in Low Power mode

This bit may be set (1) only when the core domain’s clock is up to fFLPMAX.

It may be altered only when FRE bit in SZCFG1 register is set (1).

3-1

Reserved.

IENPROG (Interrupt Enable for Program).

Interrupt request disabled.

An interrupt request to the ICU is enabled (see FMLFULL in the Flash Memory Status register).

PE (Program Enable). This bit is impact core program operations only.

Flash Programing is disabled (default)

Flash Programing is enabled (if PMER and SMER are cleared)

PMER (Page Erase). When set (1) a valid write to the on-chip flash erases the entire page pointed to by the

write address. This bit affects core erase operations only.

This bit may be modiﬁed, only when the FMBUSY bit is cleared (0); otherwise, results are undeﬁned.

Flash Page Erase is disabled (default)

Flash Page Erase is enabled (if PE and SMER are cleared).

SMER (Section Erase). When set (1), a valid write to the on-chip ﬂash erases the entire section pointed to by

the write address.

Write to a Main Block address results in a Main Block section erase.

Write to an Information Block address results in an Information Block section and its corresponding Main Block

section erase. This bit affects core erase operations only.

This bit may be modiﬁed only when the FMBUSY bit is cleared (0); otherwise, results are undeﬁned.

Flash Section Erase is disabled (default)

Flash Section Erase is enabled (if PMER and PE are cleared).

DISVRF (Disable Verify). This bit affects core program and erase operations only.

Verify flash contents after program or erase is enabled (default).

Disable the automatic verification of flash contents after program or erase.

This speeds up the program or erase speed.

15-9 Reserved.

PC87591L Datasheet(PDF) 230 Page - National Semiconductor (TI)

PC87591L Datasheet(HTML) 230 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL