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PC87591L Datasheet(PDF) 234 Page - National Semiconductor (TI) |
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PC87591L Datasheet(HTML) 234 Page - National Semiconductor (TI) |
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234 / 437 page  Embedded Controller Modules (Continued) www.national.com 234 Revision 1.07 Flash Memory Section Erase End Time Register (FLSEND) The FLSEND register controls the section erase end delay time. FTSEND defaults to (3216) on reset. Location: 00 F8DC16 Type: R/W Flash Memory Recovery Time Register (FLRCV) The FLRCV register controls the recovery time required between two accesses. FTRCV defaults to (0416) on reset. Location: 00 F8DE16 Type: R/W Bit 76543210 Name FTSEND Reset 00110010 Bit Description 7-0 FTSEND (Section Erase End Delay Count). This register should be configured based on the currently set core frequency. See Table 33 on page 223 for details of required values. Bit 76543210 Name FTRCV Reset 00000100 Bit Description 7-0 FTRCV (Recovery Time). This register should be configured based on the currently set core frequency. See Table 33 on page 223 for details of required values. |
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