PC87591L datasheet(237/437 Pages) NSC

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Embedded Controller Modules (Continued)

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If the core was executing a WAIT instruction, it resumes operation by entering an interrupt routine (an enabled interrupt in

the ICU, NMI or ISE).

Exit from Power Off

When in Power Off, activity can be resumed only by switching to Active mode. This is done by applying VCC power to the

PC87591x. The Power-Up reset sequence described in “VCC Power-Up Reset” on page 66 should be applied.

Power Mode Switch Protection

The PMC module includes a mechanism that protects the PC87591x from malfunctions caused by missing or unstable clock

signals.

Clock Toggling Indication

OHFC and OLFC bits in PMCSR register indicate the current status of the high- and low-frequency clock inputs, respectively.

The current status is based on indications from the HFCG and LFCG modules.

The PMC does not use the high-frequency clock when the OHFC bit is 0; it does not use the low-frequency clock when OLFC is 0.

During reset, the PC87591x clock does not toggle until OHFC is 1. During power mode change, if there is a request to switch

to a non-stable or non-toggling clock, the power mode change stalls.

4.17.4 The Power Management Controller Status Register (PMCSR)

For a summary of the abbreviations used for Register Type, see “Register Abbreviations and Access” on page 34.

PMCSR is a byte-wide, read/write register that selects the Active or Idle modes. In addition, it controls the operation of the

HFCG by enabling or disabling the high-frequency core clock domain. On reset, all non-reserved bits are cleared. PMCSR

format is shown below.

Location: 00 FF8016

Type: R/W

Bit

76543210

Name

OLFC

OHFC

WBPSM

Reserved

IDLE

DHF

Reserved

Reset

00000000

Bit

Description

Reserved.

DHF (Disable High-Frequency Oscillator). When cleared (0), the HFCG is enabled. In Active mode, the

HFCG is enabled regardless of the DHF value.

If in Idle mode, DHF can be used to reduce power consumption. When DHF=1, the HFCG is disabled and the

high-frequency clock is not generated. In Power off mode, the HFCG is disabled regardless of the DHF value.

DHF is cleared by the hardware when a hardware wake-up event is detected.

IDLE. When set, the core domain enters Idle mode on the execution of a WAIT instruction. WBPSM must be

set before executing the WAIT instruction.

This bit can be set and cleared by software; it is cleared by hardware when a hardware wake-up event is detected.

4-3

Reserved.

WBPSM (Wait Before Entering Power Save Mode). When set, the switch from Active to Idle mode is done by

setting the IDLE bit and executing a WAIT instruction. In addition, if DHF is set, the high-frequency oscillator is

disabled only after the WAIT instruction is executed and Idle mode is entered.

OHFC (Oscillating High-Frequency Clock).

0: Indicates that the high-frequency clock received by the PMC is either disabled, not available or not producing

a stable clock. When OHFC is cleared, the PMC does not switch to Active mode.

1: Indicates that the high-frequency clock received by the PMC is available and producing a stable clock.

OLFC (Oscillating Low-Frequency Clock).

0: Indicates that the low-frequency clock received by the PMC is either disabled, not available or not producing a

stable clock. When the OLFC is cleared, the PMC does not switch from Active mode to Power Save or Idle

modes.

1: Indicates that the low-frequency clock received by the PMC is available and producing a stable clock.

PC87591L Datasheet(PDF) 237 Page - National Semiconductor (TI)

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