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PC87591L Datasheet(PDF) 247 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part # PC87591L
Description  LPC Mobile Embedded Controllers
PDF  437 Pages
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

PC87591L Datasheet(HTML) 247 Page - National Semiconductor (TI)

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Embedded Controller Modules (Continued)
Revision 1.07
247
www.national.com
HFCG Control Register 2 (HFCGCTRL2)
The HFCGCTRL2 register sets the frequency multiplier’s operating parameters. On VCC power-up, WATCHDOG reset and
Debugger Interface reset, it is initialized to 0016.
Location: 00 FFAE16
Type: Varies per bit
Bit
76543210
Name
Reserved
96MON
MONERR
SCESTP
SCESTR
SENABLE
Reset
00000000
Bit
Type
Description
0RO
SIO ENABLE (Enable Host Domain Clock). Provides the status of the SuperI/O enable/disable
command. Any data written to this bit is ignored.
0: Disabled
1: Enabled
1
R/W1C SCESTR (SIO Clock Enable Start). Indicates that a rising edge was detected on the SENABEL
signal. When set, an interrupt is sent to the ICU (level high). Cleared by writing 1 to it. This interrupt
may be masked only in the ICU.
0: No rising edge on SENABLE was detected (default)
1: A rising edge on SENABLE was detected and an interrupt is sent to the ICU
2
R/W1C SCESTP (SIO Clock Enable Stop). Indicates that a falling edge was detected on the SENABEL
signal. When set, an interrupt is sent to the ICU (level high). Cleared by writing 1 to it. This interrupt
may be masked only in the ICU.
0: No falling edge on SENABLE was detected (default)
1: A falling edge on SENABLE was detected and an interrupt is sent to the ICU
3
R/W1C MONERR (Monitor Error). Indicates that a 48 MHz monitor error was detected during the last
WATCHDOG or Debugger Reset process. Note that this bit is cleared by all resets except WATCHDOG
and Debugger Interface resets. Once set, this bit is cleared by writing 1 to it.
0: No error detected (default)
1: 48 MHz monitor detected an out of range frequency
4RO
96MON (96 MHz Oscillations On). Indicates the oscillation frequency at which the HFCG is operating.
0: HFCG is oscillating as defined by the HFCGM and HFCGN. The core clock is identical to HFCG fre-
quency.
1: HFCG is oscillating at 96 MHz. The core clock is pre-scaled as defined by HFCGP.
7-5
Reserved.



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