PC87591L datasheet(250/437 Pages) NSC

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Embedded Controller Modules (Continued)

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TX Data Link

The Tx Data link consists of an 8-word, read/write data buffer, DBGTXD0 to DBGTXD7 registers, a read/write Status register

(DBGTXST), a read/write semaphore lock register (DBGTXLOC) and a write-only TINT control register (DBGTINT).

On Power-Up reset, the Tx Data link is reset (negating any pending message), DBGTXLOC and DBGTXST are set to their

reset values and TINT is released (1). On Warm and Internal reset, any partial message (i.e., TINT=1) is negated by setting

DBGTXLOC and DBGTXST to their reset values. Messages that were completed (i.e., TINT=0) are maintained for transmis-

sion to the host by maintaining DBGTXLOC and DBGTXST values.

On TAP reset, the data link maintain its values.

DBGTXD registers are captured by the TAP data shift register (DBGDATA) in Capture-DR state of the TAP controller when

the current Information Register (IR) is SCAN_TX. The DBGDATA length is set dynamically, according to the length field of

DBGTXST register before the Capture_DR state of the SCAN_TX operation (see Section 4.19.7 on page 260). The TAP IR

state. No parallel load is executed in Update-DR state.

The semaphore is implemented by DBGTXLOC register. A write operation, to PID field of this register, of a value other than

‘1111’ changes the contents of this field only when the PID field equals ‘1111’. This field returns to ‘1111’ in one of the fol-

lowing ways:

●

Write operation of ‘1111’ to PID ﬁeld of DBGTXLOC register from the peripheral bus while TINT is not asserted

●

Update-DR state of the TAP controller when the current instruction loaded into TAP IR register is SCAN_TX (this ac-

tion take place at the rising edge of TCK)

●

On Warm or Internal reset if TINT=1 and on Power-Up reset

A processor can access DBGTXDi registers in Active mode only. For a processor to gain ownership of the Tx link, it must

capture the DBGTXLOC semaphore using the following sequence:

1. Verify that the value of PID in DBGTXLOC register is ‘1111’.

2. Write the processor PID code to DBGTXLOC register.

3. Read DBGTXLOC. If the PID field is equal to the value that was written, the data link is granted. If not, repeat step 1.

A processor should access DBGTXDi and DBGTXST registers only after successfully gaining ownership over the Tx link by

using the above sequence.

The TINT signal is an active-low pulse asserted by the Tx data link when ASSERT bit in DBGTINT register is written with 1.

It is de-asserted, together with the semaphore indication in Update-DR state of the TAP controller, when the current instruc-

tion loaded into TAP IR register is SCAN_TX.

Access to DBGTXLOC, DBGTXST and DBGTXDi registers should be done only while TINT is not asserted. TINT negation

can be identified by the release of PID (‘1111’).

Debugger Reset Circuit

Chip reset is asserted in the Update-DR state of the TAP controller when the current instruction is ASSERT_DBG_RST. This

triggers a Debugger reset, as described in “ASSERT_DBG_RST” on page 260. This circuit is functional in Active or Idle

modes. It is functional, while TCK is not toggling, one cycle after exit from Update-DR state.

ISE Interrupt Control

The ISE interrupt control module sends ISE interrupt requests to the processor core. It consists of the write-only DBGABORT

The DBGISESRC register is cleared on PC87591x reset. During TAP reset, the values of these registers are maintained.

The DBGMASKS value is modified only in Update-DR state of the TAP controller when the current instruction is

SCAN_ABORT_MASK.

The ISE interrupt control module issues an ISE interrupt request to a specific processor or multiple processors, together with

the matched bit in DBGISESRC register, according to the MESSAGE or ABORT event.

In a MESSAGE event, an ISE interrupt is requested for a specific processor according to the PID field of the SCAN_RX

instruction. The request is issued (together with DBGISESRC bit assertion) if the current instruction loaded in TAP IR is

SCAN_RX and the TAP controller is in Update-DR state (rising edge of TCK).

An ABORT event occurs when SCAN_RX is executed with a PID of all 1s (ISE and ABORT_i bits in DBGISESRC register

are asserted) or when processor bits P_i are set in DBGABORT register by one of the processors. That is, ISE and

DBGISESRC bits are asserted with the write operation itself; if DBGABORT is written with some 0 bits, the PIDs related to

these bits do not get the ISE. In an ABORT event, the assertion of each ISE interrupt and DBGISESRC bit depends on its

masking bit in DBGMASKS register.

PC87591L Datasheet(PDF) 250 Page - National Semiconductor (TI)

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