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Further Information

The TAP is based on the test logic in the IEEE 1149.1b-1994 specification. However, since its purpose is to facilitate com-

munication, it does not support IEEE 1149.1b-1194 testing facilities. It is used here to benefit from off-the-shelf bus controller

cards and software and potential future enhancements to the test scheme.

This document includes the relevant rules of this specification. See the following documents for further information.

●

For further details and examples of the standard, see IEEE Standard Test Access Port and Boundary-Scan Architec-

ture, May 21, 1990

●

For further details of test bus chips and equipment, see the relevant manufacturer datasheets and application notes,

e.g., SCANTM Data book, National Semiconductor 400102.

●

For technical background, refer to text books on the subject, for example, Colin M. Maunder and Rodham E. Tulloss,

“The Test Access Port and Boundary-Scan Architecture”, IEEE Computer Society Press Tutorial

TAP Signals

The TAP interface signals to the JTAG serial bus are: Test Clock Input (TCK), Test Mode Select Input (TMS), Test Data Input

(TDI) and Test Data Output (TDO). The TAP controller is reset at Power-Up reset only; see Section 3.2 on page 65 for further

information.

TCK. TCK provides the clock for the JTAG serial bus and the TAP controller. Stored-state devices in the TAP maintain their

state indefinitely after the signal applied to TCK is stopped.

TMS. The TAP controller next state is set by the TMS value and its current state. The TAP samples the signal presented at

TMS on the rising edge of TCK.

Circuitry, fed from TMS, produces the same response to the application of a logic 1 as for a non-driven input.

TDI. This is the data and instructions serial input. The TAP samples the signal presented at TDI on the rising edge of TCK.

Circuitry fed from TDI produces the same response to the application of a logic 1 as for a non-driven input.

When data is shifted from TDI towards TDO, test data received at TDI appears without inversion at TDO following a number

of rising and falling edges of TCK. This is determined by the length of the instruction or Test Data register selected.

TDO. This is the data and instructions serial output. The signal driven through TDO changes its state only after the falling

edge of TCK.

The TDO driver is set to its inactive drive state, except while data or an instruction is being scanned.

TAP Controller

The TAP controller is a synchronous, finite state machine that responds to changes in the TMS and TCK signals and controls

the sequence of operations of the PC87591x reset, ISE interrupt control and data link circuitry.

Figure 82 shows the TAP controller state diagram.

PC87591L Datasheet(PDF) 254 Page - National Semiconductor (TI)