PC87591L datasheet(257/437 Pages) NSC

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Embedded Controller Modules (Continued)

Revision 1.07

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Data is not inverted between the serial input and serial output of IR.

The IR parallel input status bits, loaded at the Capture IR state of any instruction scan operation, are shown below.

Instruction Register

Operation

Table 38 shows the behavior of IR in each TAP controller state.

All actions resulting from an instruction terminate when a new instruction is transferred to the parallel output of the IR (i.e.,

in Update-IR or TAP-Reset states).

All operations of the shift register stages occur on the rising edge of TCK after entry into a TAP controller state.

Table 38. Instruction Register Operation in Each Controller State

The data present at the parallel output of the IR is latched from the shift register stage on the falling edge of TCK in Update-

IR state.

After entry into TAP-Reset state as a result of TAP controller clocked operation, the BYPASS instruction is latched onto the

IR output on the falling edge of TCK.

Bit

553210

Name

MSG_LEN

PID

RX_BUSY

Reset

Bit

Description

Fixed value (1).

Fixed value (0).

RX_BUSY (Receive Busy). Busy indication from the Rx data link.

6-3

PID (Processor ID). Contains the processor ID from the Tx data link.

When TINT is set to 1 (not active), PID ﬁeld is ‘1111’, indicating that the Tx link has no valid data.

When TINT is set to 0 (active), PID ﬁeld indicates the value of PID ﬁeld in DBGTXLOC register. Note that this

value is latched when TINT becomes active and is held until the Rx data is read by the host.

11-7

MSG_LEN (Message Length). Contains the Tx message length in words. When the Tx status word PID ﬁeld is

not ‘1111’, the MSG_LEN holds a copy of the MSG_LEN ﬁeld in DBGTXST register. When the size of this ﬁeld

is less than ﬁve bits, the MSG_LEN MSBs in the status word are forced to 0.

Controller State

Shift Register Stage

Parallel Output

TAP-Reset

Undeﬁned

Set to give BYPASS instruction

Capture-IR

Load status data (table 2-2)

Retain last state

Shift-IR

Shift towards serial output

Retain last state

Exit1-IR

Exit2-IR

Pause-IR

Retain last state

Update-IR

Retain last state

Load from shift register stage

All other states

Undeﬁned

Retain last state

PC87591L Datasheet(PDF) 257 Page - National Semiconductor (TI)

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