PC87591L datasheet(260/437 Pages) NSC

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SCAN_ABORT_MASK

The SCAN_ABORT_MASK instruction switches the data scan path to ABORT_MASK register. In Capture-DR state, a par-

allel update of the shift register occurs with the DBGMASKS values. Parallel load is performed in Update-DR state to update

the DBGMASKS values.

ASSERT_DBG_RST

A Debugger reset is asserted in Update-DR state. Serial data is switched to the BYPASS register.

4.19.7 TAP Data Registers, Debugger Interface

Bit Arrangement and Mapping

Figure 84 shows the bit allocation for a parallel load operation between any pair of serial shift registers and a peripheral bus

addressable register.

Figure 84. Bit Allocation Arrangement

Functionality in Various TAP Controller States

When data is shifted through a data register, data applied to TDI appears without inversion at TDO following an appropriate

number of TCK transitions, when the TAP controller is in Shift-DR state.

The data register connected between TDI and TDO shifts data one stage towards TDO after each rising edge of TCK in

Shift-DR state.

In TAP-Reset state, all data registers either perform their system function (if one exists) or do not interfere with the operation

of the on-chip system logic.

If, in response to the current instruction, a data register loads data from a parallel input, the data is loaded on the rising edge

of TCK following entry into Capture-DR state.

If the data register connected between TDI and TDO in response to the current instruction is provided with latched parallel

data outputs, the data is latched into the parallel output buffers on the falling edge of TCK, during Update-DR or Run-

Test/Idle states, as appropriate.

If, in response to a current instruction, no operation of a selected data register is required in a given controller state, the

When the TAP controller state machine is in TAP-Reset state during Power-Up reset, IR register is reset.

Data registers that are not selected by the current instruction are set to perform their functions, as described in Section 4.19;

specifically, see “TX Data Link” on page 250, “Debugger Reset Circuit” on page 250 and “ISE Interrupt Control” on page 250.

Table 40. Data Register Operation in Each Controller State

Controller State

Action

Capture-DR

Load data at parallel input into shift register stage. Parallel output registers, or latch, retains last state.

Shift-DR

Shift data towards serial output. Parallel output register, or latch where provided, retains state.

Exit1-DR

Exit2-DR

Pause-DR

Retain last state.

Update-DR

Load parallel output register or latch from the shift register stage. Shift register stage retains state.

All other controller

states

Registers that have a parallel output maintain the last state of this output; otherwise undeﬁned.

TDI

TDO

ADD XXXN

ADD XXX(N-1)

ADD XXX0

PC87591L Datasheet(PDF) 260 Page - National Semiconductor (TI)

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