PC87591L datasheet(263/437 Pages) NSC

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Embedded Controller Modules (Continued)

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Flash Identiﬁcation Register (FL_ID)

FL_ID is a shift register that contains device identification information. This information can help to verify the use of the cor-

rect flash programing algorithm and to match downloaded information to the device properties.

Type: Read Only

R/W1C FMDERR (Flash Data Loss Error). Indicates that a double-buffer overrun error occurred. The bit is cleared

by writing 1 to FMDERR bit in Control register. It may be cleared only when FMBUSY bit is cleared (0).

0: No data loss detected (default)

1: A write to a full buffer was detected

5RO

FLAEN (Flash Access Enabled).

0: The flash memory protection is set; read, write and erase (except special erase) are disabled

1: The flash memory access through the JTAG serial bus is enabled

6RO

BLFF (Blank Flash Flag).

0: The Blank Flash flag is cleared and the core is allowed to execute from it

1: The Blank Flash flag is set and the core is kept in reset, even when flash access is enabled

R/W

FMPRGE (Flash Memory Program Enable).

0: Programing the flash memory using JTAG write instructions is disabled (default)

1: Programing the flash memory using JTAG write instructions is enabled

R/W

FFMPERE (Flash Memory Page Erase Enable).

0: Flash page erase disabled (default)

1: Flash page erase using the JTAG Erase instruction is enabled

R/W

FMSERE (Flash Memory Sector Erase Enable).

0: Flash sector erase disabled (default)

1: Flash sector erase using the JTAG Erase instruction is enabled

R/W

FMSPERE (Flash Memory Special Erase Enable).

0: Flash special erase operation disabled (default)

1: Flash special erase operation using the JTAG Erase instructions is enabled

13-11

Reserved.

R/W

DISVRF (Disable Verify).

Enables verification of flash contents after program or erase (default)

Disables the automatic verification of flash contents after program or erase;

this speeds up the program or erase speed.

R/W

JTFIE (JTAG To Flash Interface Enabled).

0: Flash access through the JTAG is disabled. Write of 1 to any other bit in this register is ignored, all

error flags are cleared, and all other JTAG access flash transactions are ignored (i.e., Capture-DR re-

turns invalid data, Update-DR is ignored) (default).

1: Interface to the flash through the JTAG is enabled

Bit

31 30 29 28 27 26 25 24 23 2 21 20 19 18 17 16 15 14 13 12 11 10 9

Name

Reserved

SRID

SID

Reset

ID values

Bit

Type

Description

Figure 88. Flash Identiﬁcation Register

TDI

TDO

SID

FL_ID

SRID

Reserved

PC87591L Datasheet(PDF) 263 Page - National Semiconductor (TI)

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