PC87591L datasheet(266/437 Pages) NSC

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Flash Erase Register (FL_ERASE)

FL_ERASE is a shift register that starts a flash erase operation and returns the status of the erase operation. The type of

erase performed depends on the settings in the Control and Status register. The connection of the register to the serial chain

is shown in Figure 91. The FL_ERASE register is reset at Power-Up and TAP resets only.

Type: Varies per bit

Bit

Name

Error

Start/Busy

Reset

Bit

Type

Description

0RO

Busy. On read (Capture-DR), indicates the status of the flash array.

0: Flash is idle and is ready for an erase command to be started

1: Flash is busy executing a previous erase or write command; any command given at this state is ig-

nored.

Start. On write (Update-DR), starts a flash erase process.

0: Do not start a new erase process

1: Start a new erase process

1RO

Error. Indicates that an error occurred during the last erase cycle. This bit has valid data only when the

Busy bit is cleared.

0: Last erase was completed successfully (default)

1: An error was detected during the last erase. This may be due either to a failed erase or protection be-

ing set. More details about the error type are available by reading the Control and Status register.

When a value of 1 is read, this bit is cleared.

Figure 91. Flash Erase Register

TDI

TDO

Status

Control

FL_ERASE

PC87591L Datasheet(PDF) 266 Page - National Semiconductor (TI)