PC87591L datasheet(267/437 Pages) NSC

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Embedded Controller Modules (Continued)

Revision 1.07

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4.19.9 Core Registers, Debugger Interface

For a summary of the abbreviations used for Register Type, see “Register Abbreviations and Access” on page 34.

Core Register Map

Debug Receive Data Registers 0, 2, 4, 6, 8, 10, 12 and 14 (DBGRXD0-14)

DBGRXD0 to DBGRXD14 is a group of eight word-wide read-only registers. The DBGRXD0-14 registers are written from

the JTAG serial bus. They can only be read from the peripheral bus. A representative DBGRXDi register is shown below.

Location: Channel 0 - 00 FDC016

Channel 2 - 00 FDC216

Channel 4 - 00 FDC416

Channel 6 - 00 FDC616

Channel 8 - 00 FDC816

Channel 10 - 00 FDCA16

Channel 12 - 00 FDCC16

Channel 14 - 00 FDCE16

Type: RO

Mnemonic

Type

DBGRXD0-14

Debug Receive Data Registers 0, 2, 4, 6, 8, 10, 12 and 14

DBGRXST

Debug Receive Status Register

Varies per bit

DBGTXD0-14

Debug Transmit Data Registers 0, 2, 4, 6, 8, 10, 12 and 14

R/W

DBGTXLOC

Debug Transmit Lock Register

R/W

DBGTXST

Debug Transmit Status Register

R/W

DBGTINT

Debug TINT Assert Register

DBGABORT

Debug Abort Generate Register

DBGISESRCA

Debug ISE Source Register A

R/W

Bit

9876543210

Name

RX_DATAi

Bit

Description

15-0

Receive Data (RX_DATA). Data bits 16*i through 16*i+15 of the Rx data link data buffer.

PC87591L Datasheet(PDF) 267 Page - National Semiconductor (TI)

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