PC87591L datasheet(243/437 Pages) NSC

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Embedded Controller Modules (Continued)

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When transitioning from SuperI/O Enabled PMC Enabled state, there may be a transition period in which the core domain

clock is still toggling according to the setting in SuperI/O Enabled PMC Enabled state. This occurs until software method 1

is performed by the interrupt handler of the SuperI/O Disabled event.

Transition to SuperI/O Enabled PMC Disabled State

●

OSCCLK defaults to 96 MHz

●

The host domain clock is enabled and starts toggling as soon as the frequency multiplier has stabilized

●

The core domain clock is disabled (low)

Transition to SuperI/O Enabled PMC Enabled State

●

When transitioning from SuperI/O Enabled PMC Disabled state:

— OSCCLK defaults to 96 MHz

— The pre-scaler is set according to HFCGP

●

When transitioning from PMC Enabled SuperI/O Disabled state:

— Software sets OSCCLK and the pre-scaler by the LOAD96 or FAST96 command (software method 2)

●

The host domain clock is enabled and starts toggling as soon as the frequency multiplier has stabilized

●

The core domain clock is enabled and starts toggling as soon as the frequency multiplier has stabilized

When transitioning from PMC Enabled SuperI/O Disabled state, there may be a transition period in which the core domain

clock is still toggling according to the setting in PMC Enabled SuperI/O Disabled state. This occurs until software method 2

is performed by the interrupt handler of the SuperI/O Enabled event. During this transition period, the host domain clock is

still disabled.

4.18.6 48 MHz Clock Monitor

While in one of the SuperI/O Enabled states, a WATCHDOG reset or Debugger Interface reset does not interfere with the

operation of the SuperI/O. Thus, if the 48 MHz clock is correctly toggling, it is not interfered with. Toggling is monitored by

the 48 MHz clock monitor. If a violation is detected, the 48 MHz monitor error flag is set and the HFCG goes through a com-

plete reset, after which it is put into PMC Enabled SuperI/O Disabled state, ignoring the host domain enable signal.

The 48 MHz clock monitor is initiated when a WATCHDOG reset or Debugger Interface reset occurs while the HFCG is in

a SuperI/O Enabled state. The monitor checks that the host domain clock frequency is in the range of 48 MHz

±1%.

If the host domain clock frequency is in the correct range, the HFCG continues generating the 96 MHz OSCCLK, but the

programmable pre-scaler is set to a default of divide by 24. The HFCG is in SuperI/O Enabled PMC Enabled state.

The core reset routine is responsible for switching to SuperI/O Enabled PMC Enabled state and/or communicating the failure

to the host software.

4.18.7 HFCG Registers

For a summary of the abbreviations used for Register Type, see “Register Abbreviations and Access” on page 34.

HFCG Register Map

Mnemonic

Type

HFCGCTRL1

HFCG Control 1

Varies per bit

HFCGML

M Low Byte Value

R/W

HFCGMH

M High Byte Value

R/W

HFCGN

N Value

R/W

HFCGIL

I Low Byte Value

R/W

HFCGIH

I High Byte Value

R/W

HFCGP

HFCG Pre-Scaler

R/W

HFCGCTRL2

HFCG Control 2

Varies per bit

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