PC87591L datasheet(242/437 Pages) NSC

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SuperI/O Enabled State

Normal Clock Setting. This operation enables switching from PMC Enabled SuperI/O Disabled state to SuperI/O Enabled

PMC Enabled state.

To generate a 96 MHz OSCCLK, a command loads the hardwired M and N values (simultaneously) into the frequency mul-

tiplier. At the same time, the command loads the programmable pre-scaler with the value held in HFCGP register. To set a

96 MHz clock frequency and the required core clock.

1. Write the HFCGP value.

2. Set LOAD96 bit in HFCGCTRL1 register.

The HFCGN, HFCGML and HFCGMH registers are ignored and left unchanged when switching to SuperI/O Enabled states.

Fast Clock Setting. This operation enables fast switching from PMC Enabled SuperI/O Disabled state to SuperI/O Enabled

PMC Enabled state.

The HFCG maintains an internal I variable for the 96 MHz clock. The I variable is defined by two byte-wide registers: HFCGIL

and HFCGIH. In a LOAD96 operation, the frequency multiplier automatically searches for the I value needed to lock onto

the target frequency. The locking process can take several milliseconds to complete. The I variable can be recorded for the

96 MHz setting and used later to reduce the time needed for frequency locking.

To record the 96 MHz I value:

1. Write the required HFCGP value.

2. Enter any of the SuperI/O Enabled states using the Normal clock setting or Hardware clock setting process.

To fast set a 96 MHz clock frequency:

1. Write the required HFCGP value.

2. Set FAST96 bit in HFCGCTRL1 register to 1.

The HFCGN, HFCGML and HFCGMH registers are ignored and left unchanged when switching to SuperI/O Enabled states.

4.18.4 The Programmable Pre-Scaler: Core Domain Clock Generation

The core domain clock (CLK) is driven from OSCCLK via a 5-bit pre-scaler. When in PMC Enabled SuperI/O Disabled state,

the pre-scaler divides by 1. In SuperI/O Enabled PMC Disabled state, the pre-scaler is programmable, as defined in HFCGP

The core domain clock may be set in the range of 4 MHz to 20 MHz.

When LOAD96 or FAST96 bit in HFCGCTRL1 register is set (1), the pre-scaler is set to the value held in HFCGP register

(core frequency = 96 MHz / (HFCGP +1)).

When in SuperI/O Enabled PMC Enabled state, a write to HFCGP register changes the core’s frequency at the next cycle

of the pre-scaler.

When LOAD or FAST bit in HFCGCTRL1 register is set (1), the pre-scaler is automatically set to a divide by 1. The contents

of HFCGP are unchanged.

When in SuperI/O Enabled PMC Enabled state or SuperI/O Enabled PMC Disabled state, WATCHDOG reset or Debugger

Interface reset sets HFCGP to its reset value and initializes the pre-scaler using this value; see Section 4.18.6 on page 243

for details about setting the pre-scaler during state transitions.

When in Disabled state or PMC Enabled and SuperI/O Disabled state, WATCHDOG reset or Debugger Interface reset

keeps the pre-scaler in the divide by 1 operation and loads the HFCGP to its reset value.

In all states, on VCC power-up, WATCHDOG reset or Debugger Interface reset, HFCGP is set to its reset value and the pre-

scaler is set to a divide by 1.

4.18.5 State Transitions

The following section describes the actions taken by the HFCG during state transitions. Unless explicitly specified, the ac-

tions are initiated by hardware.

Transition to PMC Enabled SuperI/O Disabled State

●

When transitioning from Disabled state:

— OSCCLK defaults to a frequency set by the input data buffer (according to the most recent LOAD, FAST or Reset

command).

— The pre-scaler defaults to a divide by 1.

●

When transitioning from SuperI/O Enabled PMC Enabled state:

— Software sets OSCCLK and the pre-scaler by the LOAD or FAST command (software method 1).

●

The host domain clock is disabled (low).

●

The core domain clock is enabled and starts toggling as soon as the frequency multiplier has stabilized.

PC87591L Datasheet(PDF) 242 Page - National Semiconductor (TI)

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