AR0141CS datasheet(51/64 Pages) ONSEMI

51 / 64 page

AR0141CS/D Rev. 6, 4/16 EN

©Semiconductor Components Industries, LLC, 2016.

AR0141CS: 1/4-Inch Digital Image Sensor

Electrical Specifications

Note:

Slew rate setting = 2 for PIXCLK

Slew rate setting = 2 for parallel ports

Table 19:

I/O Timing Characteristics (2.8V VDD_IO)

Conditions: fPIXCLK=37.125 MHz (720P30fps; VDD_IO = 2.8V

Symbol

Definition

Condition

Min

Typ

Max

Unit

fEXTCLK1

Input clock frequency

PLL enabled

–

MHz

tEXTCLK1

Input clock period

PLL enabled

–

166

Input clock rise time

–

Input clock fall time

–

tRR

PIXCLK rise time

PCLK slew rate setting= 2

2.0

3.5

6.4

tFP

PIXCLK fall time

PCLK slew rate setting= 2

1.9

3.3

6.2

Clock duty cycle

tJITTER2

Input clock jitter at 27 MHz

–

600

fPIXCLK

PIXCLK frequency

default PLL configuration

37.125

74.25

MHz

tPD

PIXCLK to Data[11:0]

PCLK slew rate setting=2

parallel slew rate setting= 4

-2.0

–

5.9

tPFH

PIXCLK to FV high

PCLK slew rate setting=2

parallel slew rate setting=2

-0.9

–

4.4

tPLH

PIXCLK to LV high

PCLK slew rate setting=2

parallel slew rate setting=2

-0.8

–

4.6

tPFL

PIXCLK to FV low

PCLK slew rate setting=2

parallel slew rate setting=2

-1.5

–

3.1

tPLL

PIXCLK to FV low

PCLK slew rate setting=2

parallel slew rate setting=2

-1.5

–

3.3

CLOAD

Output load capacitance

–

CIN

Input pin capacitance

–

2.5

–

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