AR0141CS datasheet(16/64 Pages) ONSEMI

16 / 64 page

AR0141CS/D Rev. 6, 4/16 EN

©Semiconductor Components Industries, LLC, 2016.

AR0141CS: 1/4-Inch Digital Image Sensor

Pixel Sensitivity

Serial Configuration

The serial format should be configured using R0x31AC. Refer to the AR0141CS Register

Reference document for more detail regarding this register.

The serial_format register (R0x31AE) controls which serial format is in use when the

serial interface is enabled (reset_register[12] = 0). The following serial formats are

supported:

• 0x0304 - Sensor supports quad-lane HiSPi operation

• 0x0302 - Sensor supports dual-lane HiSPi operation

Pixel Sensitivity

Figure 14:

Integration Control in ERS Readout

A pixel's integration time is defined by the number of clock periods between a row's

reset and read operation. Both the read followed by the reset operations occur within a

row period (TROW) where the read and reset may be applied to different rows. The read

and reset operations will be applied to the rows of the pixel array in a consecutive order.

The coarse integration time is defined by the number of row periods (TROW) between a

row's reset and the row read. The row period is defined as the time between row read

operations (see Sensor Frame Rate).

TCOARSE = TROW * coarse_integration_time

(EQ 1)

Figure 15:

Example of 8.33ms Integration in 16.6ms Frame

Row Integration

INTEGRATION)

Row Reset

(Start of Integration)

Row Readout

Vertical Blanking

Read

Reset

Vertical Blanking

FRAME = frame_length_lines x TROW

16.6 ms = 750 rows x 22.22

μs/row

COARSE = coarse_integration_time x TROW

8.33 ms =563 rows x 22.22

μs/row

Time

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