AR0141CS datasheet(14/64 Pages) ONSEMI

14 / 64 page

AR0141CS/D Rev. 6, 4/16 EN

©Semiconductor Components Industries, LLC, 2016.

AR0141CS: 1/4-Inch Digital Image Sensor

Pixel Output Interfaces

HiSPi Physical Layer

The HiSPi physical layer is partitioned into blocks of four data lanes and an associated

clock lane. Any reference to the PHY in the remainder of this document is referring to

this minimum building block.

The PHY will serialize 12-bit data words and transmit each bit of data centered on a

rising edge of the clock, the second on the falling edge of the clock. Figure 10 shows bit

transmission. In this example, the word is transmitted in order of MSB to LSB. The

receiver latches data at the rising and falling edge of the clock.

Figure 10:

Timing Diagram

DLL Timing Adjustment

The specification includes a DLL to compensate for differences in group delay for each

data lane. The DLL is connected to the clock lane and each data lane, which acts as a

control master for the output delay buffers. Once the DLL has gained phase lock, each

lane can be delayed in 1/8 unit interval (UI) steps. This additional delay allows the user

to increase the setup or hold time at the receiver circuits and can be used to compensate

for skew introduced in PCB design.

Delay compensation may be set for clock and/or data lines in the hispi_timing register

R0x31C0. If the DLL timing adjustment is not required, the data and clock lane delay

settings should be set to a default code of 0x000 to reduce jitter, skew, and power dissipa-

tion.

Figure 11:

Block Diagram of DLL Timing Adjustment

….

MSB

LSB

TxPost

1 UI

TxPre

delay

data _lane 0

data _lane 1 clock _lane 0 data _lane 2 data _lane 3

AR0141CS Datasheet(PDF) 14 Page - ON Semiconductor