AR0141CS datasheet(29/64 Pages) ONSEMI

29 / 64 page

AR0141CS/D Rev. 6, 4/16 EN

©Semiconductor Components Industries, LLC, 2016.

AR0141CS: 1/4-Inch Digital Image Sensor

Slave Mode

Figure 26:

Slave Mode Active State and Vertical Blanking

If the slave mode is disabled, the new frame will begin after the extra delay period is

finished.

The slave mode will react to the rising edge of the input VD signal if it is in an active state.

When the VD signal is received, the sensor will begin the frame readout and the slave

mode will remain inactive for the period of one frame time plus 16 clock periods

(TFRAME + (16 / CLK_PIX)). After this period, the slave mode will re-enter the active state

and will respond to the VD signal.

Start of frame N

End of frame N

Start of frame N + 1

Frame Valid

OB Rows (2, 4, or 8 rows)

Embedded Data Row (2 rows)

Active Data Rows

Blank Rows or Embedded stats (2 rows)

Extra Vertical Blanking

(frame_length_lines - min_frame_length_lines)

VD Signal

Slave Mode Active State

The period between the

rising edge of the VD signal

and the slave mode ready

state is T

FRAME + 16 clocks.

Extra Delay (clocks)

AR0141CS Datasheet(PDF) 29 Page - ON Semiconductor