ML7396AB datasheet(108/140 Pages) LAPIS

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FEDL7396A/B/E-07

ML7396A/B/E

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●CCA operation

●Normal mode

CCA normal mode will be executed by issueing RX_ON by [RF_STATUS:B0 0x6C] register after setting CCA_EN

([CCA_CNTRL:B0 0x15(4)])=0b1, CCA_IDLE_EN ([CCA_CNTRL:B0 0x15(3)])=0b0 and CCA_LOOP_START

([CCA_CNTRL:B0 0x15(5)])=0b0. Compariing acquired ED average value with CCA threshold value in [CCA_LEVEL:B0

0x13] register and notice the result. After CCA execution, CCA_EN is turned disabled, and RF maintains RX_ON state.

Even if set CCA_EN=0b1 during RX_ON state, CCA can be performed by. However, in this case, 16μs - 32μs (2 cycle of

A/D conversion) WAIT is automatically added as the filter stabilization period before CCA execution. (If CCA_EN=0b1 is

set before issuing RX_ON, WAIT is not added because filter stabilization period is included in RF transition period.)

If bit synchronization is detected during CCA, keep receiving with wider BPF bandwidth for CCA operation. If CCA is

executed after bit synchronization detection, CCA is executed with normal BPF bandwidth.

CCA execution is also possible during diversity search. In this case, after CCA completion diversity search will be resumed

automatically.

START

Yes

CCA setting

[CCA_CNTRL:B0 0x15(5-3)]

CCA_LOOP_START=0b0

CCA_EN=0b1

CCA_IDLE_EN=0b0

RX_ON issue

CCA start

[RF_STATUS:B0 0x6C]

CCA completion (INT[08])?

[INT_SOURCE_GRP2:B0 0x25]

Read CCA_RSLT[1:0]

[CCA_CNTRL:B0 0x15(1-0)]

Set CCA_EN=0b1

[CCA_CNTRL:B0 0x15(4)]

Clear INT[08]

[INT_SOURCE_GRP2:B0 0x25]

Stop CCA?

TRX_OFF issue

[RF_STATUS:B0 0x6C]

END

ML7396AB Datasheet(PDF) 108 Page - LAPIS Semiconductor Co., Ltd.