ML7396AB datasheet(104/140 Pages) LAPIS

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FEDL7396A/B/E-07

ML7396A/B/E

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●Address Filter

When Address filtering function is enabled, if receiving packet which address field are mismatch, Packet discard completion

interrupt (INT[03] group1) will be generated. At this time, if ADDFIL_NG_SET ([PACKET_MODE_SET:B0 0x45(5)]) =0b0,

aborting packet data immediately after address mismatch detection and CRC error interrupt (INT[20]/[21] group3) is also

generated at the same time. (The details of interrupt notifiaction, please refer to the [Interrupts timing when using

INT_TIM_CTRL] in “Address filtering function”.) After notifying Packet discard completion interrupt and CRC error

interrupt, it is need to clear FIFO by [INT_SOURCE_GRP1:B0 0x24] register or reading out data specified by Lngth field from

the FIFO, in order to store next packet to right FIFO. After that, clearing Packet discard completion interrupt and CRC error

interrupt, and then waiting next packet.

START

RX_ON issue

[RF_STATUS:B0 0x6C]

For deteils of process after receiving ACK packet, please refer

[AUTO_ACK_SET:B0 0x55] register description (*4) and

TX mode (Ack receiving with addrsss filter) flowchart.

Address filtering setting

ADDFIL_NG_SET=0b0 (B0 0x45(5))

[ADDFIL_CNTRL:B2 0x60]

[PANID_L/H:B2 0x61,62]

[64ADDR1-8:B2 0x63-6A]

[SHT_ADDR0_L/H:B2 0x6B,6C]

[SHT_ADDR1_L/H:B2 0x6D.6E]

Packet discard completion?

(INT[03])

[INT_SOURCE_GRP1:B0 0x24]

Yes

Read RX data from FIFO

[RD_RX_FIFO:B0 0x7F]

Clear interrupts

INT[18],[20] or INT[19].[21]

[INT_SOURCE_GRP3:B0 0x26]

Next packet RX?

END

TRX_OFF issue

[RF_STATUS:B0 0x6C]

Yes

RX completion?

(INT[18]/[19])

[INT_SOURCE_GRP3:B0 0x26]

Yes

CRC Error?

Confirming FIFO filed which CRC

error occurs.

(INT[20]/[21])

[INT_SOURCE_GRP3:B0 0x26]

Yes

If ADDFIL_NG_SET=0b1,

When Packet discard cpmletion is

generated, PHY reset should be

required.

Clear FIFO which CRC error occurs

[INT_SOURCE_GRP1:B0 0x24 (7 or 6)]

If CRC error interrupt occurs at the

same time, following process is same

as described in the flowchart.

Clear interrupts

INT[03]

[INT_SOURCE_GRP1:B0 0x24]

INT[20] or INT[21]

[INT_SOURCE_GRP3:B0 0x26

[Note]

When executing PHY reset during address filtering

function, any interrupt procedure should be done.

When executing PHY reset, if reading data is remaining in

a FIFO, this data will also be cleard and discarded packet

counter is reset to 0.

ML7396AB Datasheet(PDF) 104 Page - LAPIS Semiconductor Co., Ltd.

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