ML7396AB datasheet(102/140 Pages) LAPIS

102 / 140 page

FEDL7396A/B/E-07

ML7396A/B/E

102/140

●ACK TX mode (AUTO_ACK, packet length ≥ 257 bytes)

START

Set AUTO_ACK_EN=0b1

[AUTO_ACK_SET:B0 0x55(4)]

RX FIFO trigger level setting

[RX_ALARM_LH:B0 0x37] =0x00

[RX_ALARM_HL:B0 0x38] =0x00

Yes

CRC error (INT[20]/INT[21])?

[INT_SOURCE_GRP3:B0 0x26]

RX_ON issue

[RF_STATUS:B0 0x6C]

Clear INT[20] or [21]

Read pending data

[INT_SOURCE_GRP3:B0 0x26]

Yes

FIFO-Full (INT[05])?

[INT_SOURCE_GRP1:B0 0x24]

PHY reset issue

[RST_SET:B0 0x01]

From RX flowchart (≥257 byte)

Read RX data from FIFO

[RD_RX_FIFO:B0 0x7F]

PHY reset issue

[RST_SET:B0 0x01]

Set ACK_STOP=0b1

[AUTO_ACK_SET:B0 0x55(0)]

Set ACK_STOP=0b0

[AUTO_ACK_SET:B0 0x55(0)]

END

(*1)

Set ACK_STOP=0b1

[AUTO_ACK_SET:B0 0x55(0)]

(*1)

Set ACK_STOP=0b0

Address match?

[AUTO_ACK_SET:B0 0x55(0)]

Yes

END

Ack frame setting

Auto Ack ready (INT[24])?

[INT_SOURCE_GRP4:B0 0x27]

[ACK_FRAME1:B0 0x53]

[ACK_FRAME2:B0 0x54]

Yes

When using Ack timer, no need

to set ACK_SEND bit.

Set ACK_SEND=0b1

[AUTO_ACK_SET:B0 0x55(1)]

TX completion?

(INT[16]/[17])

[INT_SOURCE_GRP3:B0 0x26]

RX completion?

(INT[18]/[19])

Yes

[INT_SOURCE_GRP3:B0 0x26]

Clear interrupts

Yes

INT[16],[22] or INT[17].[23]

[INT_SOURCE_GRP3:B0 0x26]

Set ACK_STOP=0b1

[AUTO_ACK_SET:B0 0x55(0)]

(*1)

Only when data rate is 50kbps and SCLK speed is

16MHz (max), please set 12μs wait between

ACK_STOP=0b1 to ACK_STOP=0b0.

Set ACK_STOP=0b0

[AUTO_ACK_SET:B0 0x55(0)]

END

ML7396AB Datasheet(PDF) 102 Page - LAPIS Semiconductor Co., Ltd.

ML7396AB Datasheet(HTML) 102 Page - LAPIS Semiconductor Co., Ltd.

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