ML7396AB datasheet(105/140 Pages) LAPIS

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FEDL7396A/B/E-07

ML7396A/B/E

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●FIFO Clear (Rx)

When RX completion interrupt (INT[18]/[19] group3) and CRC error interrupt (INT[20]/[21] group 3) is notified in the same

time, clearing FIFO by set 0b0 to FIFO_CLR0/1 ([INT_SOURCE_GRP1:B0 0x24(6/7)]) if no need to read remaining RX data.

And then clearing RX completion interript and CRC error interrupt.

If receiving next packet, keeping RX_ON state. If terminating RX_ON state, please issueing TRX_OFF command by

[RF_STATUS:B0 0x6C] register. Be sure to clear the correct FIFO bank only. Alternatively, FIFO can be cleared by issueing

PHY reset by using [RST_SET:B0 0x01] register.

START

RX FIFO trigger level setting

[RX_ALARM_LH:B0 0x37] =0x00

[RX_ALARM_HL:B0 0x38] =0x00

RX_ON issue

[RF_STATUS:B0 0x6C]

FIFO-Full (INT[05])?

[INT_SOURCE_GRP1:B0 0x24]

Yes

Read RX data from FIFO

[RD_RX_FIFO:B0 0x7F]

Yes

RX completion (INT[18]/[19])?

[INT_SOURCE_GRP3:B0 0x26]

CRC error (INT[20]/INT[21])?

[INT_SOURCE_GRP3:B0 0x26]

Read RX data from FIFO

[RD_RX_FIFO:B0 0x7F]

Yes

Clear FIFO

[INT_SOURCE_GRP1:B0 0x24(6,7)]

Yes

Read out Rx data

Alternatively issueing

PHY reset.

Clear interrupts

Note:

INT[18],[20] or INT[19].[21]

Be sure to clear the correct FIFO bank.

[INT_SOURCE_GRP3:B0 0x26]

When issuing PHY reset, both FIFOs are

cleard.

Next packet RX?

TRX_OFF issue

[RF_STATUS:B0 0x6C]

END

ML7396AB Datasheet(PDF) 105 Page - LAPIS Semiconductor Co., Ltd.

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