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DS2155 Datasheet(PDF) 243 Page - Dallas Semiconductor |
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DS2155 Datasheet(HTML) 243 Page - Dallas Semiconductor |
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243 / 262 page  DS2156 243 of 262 Figure 34-19. Transmit-Side Boundary Timing (Elastic Store Disabled) Note 1: TSYNC is in the output mode (IOCR1.1 = 1). Note 2: TSYNC is in the input mode (IOCR1.1 = 0). Note 3: TCHBLK is programmed to block channel 2. Note 4: TLINK is programmed to source the Sa4 bit. Note 5: The signaling data at TSIG during channel 1 is normally overwritten in the transmit formatter with the CAS MF alignment nibble (0000). Note 6: Shown is a TNAF frame boundary. Figure 34-20. Transmit-Side Boundary Timing, TSYSCLK = 1.544MHz (Elastic Store Enabled) Note 1: The F-bit position in the TSER data is ignored. Note 2: TCHBLK is programmed to block channel 24. LSB MSB LSB MSB CHANNEL 1 CHANNEL 2 CHANNEL 1 CHANNEL 2 ABC D TCLK TSER TSYNC TSYNC TSIG TCHCLK TCHBLK TLCLK TLINK 1 2 3 4 DON'T CARE Si 1 A Sa4 Sa5 Sa6 Sa7 Sa8 D DON'T CARE 4 LSB F MSB LSB MSB CHANNEL 1 CHANNEL 24 TSYSCLK TSER TSSYNC TCHCLK TCHBLK CHANNEL 23 1 2 |
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