DS2155 datasheet(239/262 Pages) DALLAS

Part #	DS2155

Description	T1/E1/J1 Single-Chip Transceiver TDM/UTOPIA II Interface

PDF	262 Pages

Scroll/Zoom	100%

Manufacturer	DALLAS [Dallas Semiconductor]

Direct Link	https://www.maximintegrated.com/en.html

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DS2156

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Figure 34-13. Receive-Side Boundary Timing, RSYSCLK = 1.544MHz (Elastic

Store Enabled)

Note 1: Data from the E1 channels 1, 5, 9, 13, 17, 21, 25, and 29 is dropped (channel 2 from the E1 link is mapped to channel 1 of the T1 link,

etc.) and the F-bit position is added (forced to on 1).

Note 2: RSYNC in the output mode (IOCR1.4 = 0).

Note 3: RSYNC in the input mode (IOCR1.4 = 1).

Note 4: RCHBLK is programmed to block channel 24.

Figure 34-14. Receive-Side Boundary Timing, RSYSCLK = 2.048MHz (Elastic

Store Enabled)

Note 1: RSYNC is in the output mode (IOCR1.4 = 0).

Note 2: RSYNC is in the input mode (IOCR1.4 = 1).

Note 3: RCHBLK is programmed to block channel 1.

Note 4: RSIG normally contains the CAS multiframe alignment nibble (0000) in channel 1.

RSER

CHANNEL 23/31

CHANNEL 24/32

CHANNEL 1/2

RCHCLK

RCHBLK

RSYSCLK

RSYNC

RMSYNC

LSB

MSB

LSB

RSER

CHANNEL 1

RCHCLK

RCHBLK

RSYSCLK

RSYNC

CHANNEL 31

CHANNEL 32

RSYNC

RMSYNC

RSIG

CHANNEL 31

CHANNEL 32

CHANNEL 1

LSB MSB

Note 4

DS2155 Datasheet(PDF) 239 Page - Dallas Semiconductor

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