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DS2155 Datasheet(PDF) 235 Page - Dallas Semiconductor |
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DS2155 Datasheet(HTML) 235 Page - Dallas Semiconductor |
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235 / 262 page ![]() DS2156 235 of 262 Figure 34-5. Receive-Side 2.048MHz Boundary Timing (with Elastic Store Enabled) Note 1: RSER data in channels 1, 5, 9, 13, 17, 21, 25, and 29 are forced to 1. Note 2: RSYNC is in the output mode (IOCR1.4 = 0). Note 3: RSYNC is in the input mode (IOCR1.4 = 1). Note 4: RCHBLK is forced to 1 in the same channels as RSER (see Note 1). Note 5: The F-bit position is passed through the receive-side elastic store. Figure 34-6. Transmit-Side D4 Timing Note 1: TSYNC in the frame mode (IOCR1.2 = 0) and double-wide frame sync is not enabled (IOCR1.1 = 0). Note 2: TSYNC in the frame mode (IOCR1.2 = 0) and double-wide frame sync is enabled (IOCR1.1 = 1). Note 3: TSYNC in the multiframe mode (IOCR1.2 = 1). Note 4: TLINK data (Fs bits) is sampled during the F-bit position of even frames for insertion into the outgoing T1 stream when enabled through T1TCR1.2. RSER CHANNEL 1 RCHCLK RCHBLK RSYSCLK RSYNC CHANNEL 31 CHANNEL 32 1 3 4 RSYNC 2 RMSYNC RSIG CHANNEL 31 CHANNEL 32 B A C/A D/B C/A D/B AB CHANNEL 1 LSB MSB LSB 1 2345 67 89 10 11 12 12 345 1 2 3 4 TSSYNC FRAME# TLCLK TSYNC TSYNC TSYNC TLINK |
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