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DS2155 Datasheet(PDF) 234 Page - Dallas Semiconductor |
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DS2155 Datasheet(HTML) 234 Page - Dallas Semiconductor |
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234 / 262 page  DS2156 234 of 262 Figure 34-3. Receive-Side Boundary Timing (with elastic store disabled) Note 1: RCHBLK is programmed to block channel 24. Note 2: Shown is RLINK/RLCLK in the ESF framing mode. Figure 34-4. Receive-Side 1.544MHz Boundary Timing (with Elastic Store Enabled) Note 1: RSYNC is in the output mode (IOCR1.4 = 0). Note 2: RSYNC is in the input mode (IOCR1.4 = 1). Note 3: RCHBLK is programmed to block channel 24. CHANNEL 23 CHANNEL 24 CHANNEL 1 CHANNEL 23 CHANNEL 24 CHANNEL 1 RCLK RSER RSYNC RFSYNC RSIG RCHCLK RCHBLK1 RLCLK RLINK 2 B A C/A D/B A C/A D/B LSB F MSB MSB LSB AB RSER CHANNEL 23 CHANNEL 24 CHANNEL 1 RCHCLK RCHBLK RSYSCLK RSYNC2 3 RSYNC1 RMSYNC RSIG LSB F MSB MSB LSB CHANNEL 23 CHANNEL 24 CHANNEL 1 B A C/A D/B A C/A D/B AB |
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