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DS2155 Datasheet(PDF) 236 Page - Dallas Semiconductor |
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DS2155 Datasheet(HTML) 236 Page - Dallas Semiconductor |
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236 / 262 page ![]() DS2156 236 of 262 Figure 34-7. Transmit-Side ESF Timing Note 1: TSYNC in frame mode (IOCR1.2 = 0) and double-wide frame sync is not enabled (IOCR1.3 = 0). Note 2: TSYNC in frame mode (IOCR1.2 = 0) and double-wide frame sync is enabled (IOCR1.3 = 1). Note 3: TSYNC in multiframe mode (IOCR1.2 = 1). Note 4: TLINK data (FDL bits) sampled during the F-bit time of odd frame and inserted into the outgoing T1 stream if enabled through TCR1.2. Note 5: ZBTSI mode is enabled (T1TCR2.1 = 1). Note 6: TLINK data (Z bits) sampled during the F-bit time of frames 1, 5, 9, 13, 17, and 21 and inserted into the outgoing stream if enabled through T1TCR1.2. Figure 34-8. Transmit-Side Boundary Timing (with Elastic Store Disabled) Note 1: TSYNC is in the output mode (IOCR1.1 = 1). Note 2: TSYNC is in the input mode (IOCR1.1 = 0). Note 3: TCHBLK is programmed to block channel 2. Note 4: Shown is TLINK/TLCLK in the ESF framing mode. 1 2345 6789 10 11 12 1 2 3 6 TSSYNC FRAME# TLCLK TSYNC TSYNC TSYNC TLINK 13 14 15 16 17 18 19 20 21 22 23 24 1 2345 4 TLCLK TLINK 5 LSB F MSB LSB MSB LSB MSB CHANNEL 1 CHANNEL 2 CHANNEL 1 CHANNEL 2 AB C/A D/B AB C/A D/B TCLK TSER TSYNC TSYNC TSIG TCHCLK TCHBLK TLCLK TLINK D/B 1 2 3 4 DON'T CARE |
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