DS2155 datasheet(238/262 Pages) DALLAS

Part #	DS2155

Description	T1/E1/J1 Single-Chip Transceiver TDM/UTOPIA II Interface

PDF	262 Pages

Scroll/Zoom	100%

Manufacturer	DALLAS [Dallas Semiconductor]

Direct Link	https://www.maximintegrated.com/en.html

Logo

238 / 262 page

DS2156

238 of 262

34.2 E1 Mode

Figure 34-11. Receive-Side Timing

Note 1: RSYNC in frame mode (IOCR1.5 = 0).

Note 2: RSYNC in multiframe mode (IOCR1.5 = 1).

Note 3: RLCLK is programmed to output just the Sa bits.

Note 4: RLINK always outputs all five Sa bits as well as the rest of the receive data stream.

Note 5: This diagram assumes the CAS MF begins in the RAF frame.

Figure 34-12. Receive-Side Boundary Timing (with Elastic Store Disabled)

Note 1: RCHBLK is programmed to block channel 1.

Note 2: RLCLK is programmed to mark the Sa4 bit in RLINK.

Note 3: Shown is a RNAF frame boundary.

Note 4: RSIG normally contains the CAS multiframe alignment nibble (0000) in channel 1.

CHANNEL 32

CHANNEL 1

CHANNEL 2

CHANNEL 32

CHANNEL 1

CHANNEL 2

RCLK

RSER

RSYNC

RFSYNC

RSIG

RCHCLK

RCHBLK

RLCLK

RLINK

LSB

MSB

A Sa4 Sa5 Sa6 Sa7 Sa8

Sa4 Sa5 Sa6 Sa7 Sa8

Note 4

FRAME#

3456

789

12 13

RLINK

RLCLK

RSYNC

RFSYNC

DS2155 Datasheet(PDF) 238 Page - Dallas Semiconductor

DS2155 Datasheet(HTML) 238 Page - Dallas Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL