DS2155 datasheet(255/262 Pages) DALLAS

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DS2156

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36.3 Receive-Side AC Characteristics

AC CHARACTERISTICS: RECEIVE SIDE

(Figure 36-8, Figure 36-9, and Figure 36-10)

(VDD = 3.3V

±5%, TA = 0°C to +70°C for DS2156L; VDD = 3.3V ±5%, TA = -40°C to +85°C for DS2156LN.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

488 (E1)

RCLKO Period

tLP

648 (T1)

tLH

(Note 1)

200

0.5 tLP

RCLKO Pulse Width

tLL

(Note 1)

200

0.5 tLP

tLH

(Note 2)

150

0.5 tLP

RCLKO Pulse Width

tLL

(Note 2)

150

0.5 tLP

488 (E1)

RCLKI Period

tCP

648 (T1)

tCH

0.5 tCP

RCLKI Pulse Width

tCL

0.5 tCP

(Note 3)

648

(Note 4)

488

(Note 5)

244

(Note 6)

122

RSYSCLK Period

tSP

(Note 7)

tSH

0.5 tSP

RSYSCLK Pulse Width

tSL

0.5 tSP

RSYNC Setup to RSYSCLK Falling

tSU

RSYNC Pulse Width

tPW

RPOSI/RNEGI Setup to RCLKI Falling

tSU

RPOSI/RNEGI Hold From RCLKI

Falling

tHD

RSYSCLK, RCLKI Rise and Fall Times

tR, tF

Delay RCLKO to RPOSO, RNEGO Valid

tDD

Delay RCLK to RSER, RDATA, RSIG,

RLINK Valid

tD1

Delay RCLK to RCHCLK, RSYNC,

RCHBLK, RFSYNC, RLCLK

tD2

Delay RSYSCLK to RSER, RSIG Valid

tD3

Delay RSYSCLK to RCHCLK,

RCHBLK, RMSYNC, RSYNC

tD4

Note 1: Jitter attenuator enabled in the receive path.

Note 2: Jitter attenuator disabled or enabled in the transmit path.

Note 3: RSYSCLK = 1.544MHz

Note 4: RSYSCLK = 2.048MHz

Note 5: RSYSCLK = 4.096MHz

Note 6: RSYSCLK = 8.192MHz

Note 7: RSYSCLK = 16.384MHz

DS2155 Datasheet(PDF) 255 Page - Dallas Semiconductor

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