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DS2155 Datasheet(PDF) 259 Page - Dallas Semiconductor |
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DS2155 Datasheet(HTML) 259 Page - Dallas Semiconductor |
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259 / 262 page ![]() DS2156 259 of 262 Figure 36-11. Transmit-Side Timing Note 1: TSYNC is in the output mode (IOCR1.1 = 1). Note 2: TSYNC is in the input mode (IOCR1.1 = 0). Note 3: TSER is sampled on the falling edge of TCLK when the transmit-side elastic store is disabled. Note 4: TCHCLK and TCHBLK are synchronous with TCLK when the transmit-side elastic store is disabled. Note 5: In E1 mode, TLINK is only sampled during Sa bit locations as defined in E1TCR2; no relationship between TLCLK/TLINK and TSYNC is implied. t F t R 1 TCLK TSER / TSIG / TDATA TCHCLK t t CL t CH CP TSYNC TSYNC TLINK TLCLK TCHBLK t D2 tD2 tD2 t t t t t t HD SU D2 SU HD D1 tHD 2 5 TESO tSU |
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