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DS2155 Datasheet(PDF) 258 Page - Dallas Semiconductor

Part # DS2155
Description  T1/E1/J1 Single-Chip Transceiver TDM/UTOPIA II Interface
PDF  262 Pages
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Manufacturer  DALLAS [Dallas Semiconductor]
Direct Link  https://www.maximintegrated.com/en.html
Logo DALLAS - Dallas Semiconductor

DS2155 Datasheet(HTML) 258 Page - Dallas Semiconductor

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DS2156
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36.4 Transmit AC Characteristics
AC CHARACTERISTICS: TRANSMIT SIDE
(Figure 36-11, Figure 36-12, and Figure 36-13)
(VDD = 3.3V
±5%, TA = -40°C to +85°C for DS2156L; VDD = 3.3V ±5%, TA = 0°C to +70°C for DS2156LN)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP (E1)
MAX
UNITS
488 (E1)
TCLK Period
tCP
648 (T1)
ns
tCH
20
0.5 tCP
TCLK Pulse Width
tCL
20
0.5 tCP
ns
488 (E1)
TCLKI Period
tLP
648 (T1)
ns
tLH
20
0.5 tLP
TCLKI Pulse Width
tLL
20
0.5 tLP
ns
(Note 8)
648
(Note 9)
448
(Note 10)
244
(Note 11)
122
TSYSCLK Period
tSP
(Note 12)
61
ns
20
0.5 tSP
TSYSCLK Pulse Width
tSP
20
0.5 tSP
ns
TSYNC or TSSYNC Setup to TCLK or
TSYSCLK Falling
tSU
20
ns
TSYNC or TSSYNC Pulse Width
tPW
50
ns
TSER, TSIG, TDATA, TLINK, TPOSI,
TNEGI Setup to TCLK, TSYSCLK,
TCLKI Falling
tSU
20
ns
TSER, TSIG, TDATA, TLINK Hold
from TCLK or TSYSCLK Falling
tHD
20
ns
TPOSI, TNEGI Hold from TCLKI
Falling
tHD
20
ns
TCLK, TCLKI or TSYSCLK Rise and
Fall Times
tR, tF
25
ns
Delay TCLKO to TPOSO, TNEGO
Valid
tDD
50
ns
Delay TCLK to TESO, UT-UTDO
Valid
tD1
50
ns
Delay TCLK to TCHBLK, TCHCLK,
TSYNC, TLCLK
tD2
50
ns
Delay TSYSCLK to TCHCLK,
TCHBLK
tD3
22
ns
Note 8: TSYSCLK = 1.544MHz
Note 9: TSYSCLK = 2.048MHz
Note 10: TSYSCLK = 4.096MHz
Note 11: TSYSCLK = 8.192MHz
Note 12: TSYSCLK = 16.384MHz



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