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DS2155 Datasheet(PDF) 257 Page - Dallas Semiconductor |
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DS2155 Datasheet(HTML) 257 Page - Dallas Semiconductor |
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257 / 262 page ![]() DS2156 257 of 262 Figure 36-9. Receive-Side Timing, Elastic Store Enabled Note 1: RSYNC is in the output mode. Note 2: RSYNC is in the input mode. Note 3: F-bit when MSTRREG.1 = 0, MSB of TS0 when MSTREG.1 = 1. Figure 36-10. Receive Line Interface Timing F t tR tD3 tD4 tD4 t D4 t tSU HD RSER / RSIG RCHCLK RCHBLK 1 RSYNC 2 RSYNC RSYSCLK SL t tSP SH t t D4 RMSYNC SEE NOTE 3 t F t R RPOSI, RNEGI RCLKI CL t tCP CH t tSU tHD tDD RPOSO, RNEGO RCLKO LL t tLP LH t |
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