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DS2155 Datasheet(PDF) 256 Page - Dallas Semiconductor |
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DS2155 Datasheet(HTML) 256 Page - Dallas Semiconductor |
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256 / 262 page ![]() DS2156 256 of 262 Figure 36-8. Receive-Side Timing Note 1: RSYNC is in the output mode. Note 2: Shown is RLINK/RLCLK in the ESF framing mode. Note 3: No relationship between RCHCLK and RCHBLK and other signals is implied. Note 4: RLCLK only pulses high during Sa bit locations as defined in the E1RCR2 register. tD1 1 tD2 RSER / RDATA / RSIG RCHCLK RCHBLK RSYNC RLCLK RLINK (T1MODE) tD1 RCLK RFSYNC / RMSYNC 2 tD2 tD2 tD2 tD2 RLINK (E1 MODE) Sa4 to Sa8 Bit Position 4 1ST FRAME BIT |
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