PM5344 datasheet(32/212 Pages) PMC

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PM5344 SPTX

DATA SHEET

PMC-930531

ISSUE 6

SONET/SDH PATH TERMINATING TRANSCEIVER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

Pin Name

Type

No.

Function

DC1J1V1

Output

The DROP bus composite timing signal (DC1J1V1) indicates the frame, payload

and tributary multiframe boundaries on the DROP data bus DD[7:0]. DC1J1V1

pulses high with the DROP bus payload active signal (DPL) set low to mark the first

STS-1 Identification byte or equivalently the STM identification byte (C1).

DC1J1V1 pulses high with DPL set high to mark the path trace byte (J1).

Optionally, the DC1J1V1 signal pulses high on the V1 byte to indicate tributary

multiframe boundaries. DC1J1V1 is updated on the rising edge of DCK.

DDP

Output

The DROP bus data parity signal (DDP) indicates the parity of the DROP bus

signals. The DROP data bus (DD[7:0]) is always included in parity calculations.

The internal register bits control the inclusion of the DPL and DC1J1V1 signals in

parity calculation and the sense (odd/even) of the parity. DDP is updated on the

rising edge of DCK.

ACK

Input

110

The ADD bus clock (ACK) provides timing for the ADD bus and the GENERATED

bus interfaces. ACK is nominally a 19.44 MHz or 6.48 MHz, 50% duty cycle clock.

Inputs AD[7:0], APL, AC1J1V1, GFP and GMFP are sampled on the rising edge of

ACK. Outputs GPL, GC1J1V1, and GD[1:0] are updated on the rising edge of

ACK.

AD[7]

AD[6]

AD[5]

AD[4]

AD[3]

AD[2]

AD[1]

AD[0]

Input

111

112

113

114

115

116

117

118

The ADD bus data (AD[7:0]) contains the SONET/SDH transmit payload data. The

transport overhead bytes, including the H1, H2 pointer bytes, are ignored. The

phase relation of the SPE (VC) to the transport frame is determined by the ADD

bus composite timing signal (AC1J1V1). AD[7] is the most significant bit

(corresponding to bit 1 of each serial word, the first bit transmitted). AD[0] is the

least significant bit (corresponding to bit 8 of each serial word, the last bit

transmitted). AD[7:0] is sampled on the rising edge of ACK.

APL

Input

120

The ADD bus payload active signal (APL) indicates when AD[7:0] is carrying a

payload byte. It is set high during path overhead and payload bytes and low during

transport overhead bytes. APL is set high during the H3 byte to indicate a negative

pointer justification event and set low during the byte following H3 to indicate a

positive pointer justification event. APL is sampled on the rising edge of ACK.

AC1J1V1

Input

119

The ADD bus composite timing signal (AC1J1V1) identifies the frame, payload and

tributary multiframe boundaries on the ADD data bus AD[7:0]. AC1J1V1 pulses

high with the ADD bus payload active signal (APL) set low to mark the first STS-1

Identification byte or equivalently the STM identification byte (C1). AC1J1V1

pulses high with APL set high to mark the path trace byte (J1). The AC1J1V1

signal pulses high on the V1 byte to indicate tributary multiframe boundaries.

AC1J1V1 is sampled on the rising edge of ACK.

PM5344 Datasheet(PDF) 32 Page - PMC-Sierra, Inc

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