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PM5344 Datasheet(PDF) 55 Page - PMC-Sierra, Inc

Part # PM5344
Description  SONET/SDH PATH TERMINATING TRANSCEIVER TELECOM
PDF  212 Pages
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Manufacturer  PMC [PMC-Sierra, Inc]
Direct Link  http://www.pmc-sierra.com
Logo PMC - PMC-Sierra, Inc

PM5344 Datasheet(HTML) 55 Page - PMC-Sierra, Inc

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PM5344 SPTX
DATA SHEET
PMC-930531
ISSUE 6
SONET/SDH PATH TERMINATING TRANSCEIVER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
41
path AIS is immediately inserted on detection of ISF and removed on detection
of inactive ISF code.
9.6
Transmit Path Trace Buffer
The transmit portion of the SONET Path Trace Buffer (SPTB) sources the path
trace identifier message (J1) for the Transmit Overhead Processor block. The
length of the trace message is selectable between 16 bytes and 64 bytes. The
SPTB contains one page of transmit trace identifier message memory. Identifier
message data bytes are written by the microprocessor into the message buffer
and delivered serially to the Transmit Overhead Processor block for insertion in
the transmit stream. When the microprocessor is updating the transmit page
buffer, SPTB may be programmed to transmit null characters to prevent
transmission of partial messages.
9.7
Telecombus Interface
The Telecombus Interface block converts signals defined in the Telecombus
standard to those useable by TSBs. It performs multiplexing and demultiplexing
functions in STS-3 (AU3) mode to deliver and collect data at STS-1 rate from the
three Receive Telecombus Aligner and Transmit Transport Overhead Processors
to the STS-3 line rate. To accommodate unequipped application on the ADD
bus, the Telecombus Interface block may be programmed to set the ADD bus
SPE bytes to all ones. When line loopback is enabled, the Telecombus Interface
block replaces the data received on the ADD bus by the data placed on the
DROP bus.
9.8
Microprocessor Interface
The microprocessor interface block provides normal and test mode registers, and
the logic required to connect to the microprocessor interface. The normal mode
registers are required for normal operation, and test mode registers are used to
enhance the testability of the SPTX. The register set is accessed as follows:
9.9
Register Memory Map
Table 3
- Register Memory Map
Address
Register
00H
SPTX Master Configuration
01H
SPTX Master Alarm Configuration



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